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* Disable traversal limit when reading logical netlist.Keith Rothman2021-02-171-1/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial site router.Keith Rothman2021-02-174-6/+813
| | | | | | | | This site router likely cannot handle the full problem space. It may need to be replaced with a more generalize approach as testing continues. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working on standing up initial constraints system.Keith Rothman2021-02-173-25/+468
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* clangformatgatecat2021-02-171-3/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #586 from litghost/add_cell_bel_mapping_onlygatecat2021-02-172-13/+274
|\ | | | | Add Cell -> BEL Pin maps to FPGA interchange arch.
| * Require `--package` when arch BBA contains multiple packages.Keith Rothman2021-02-161-3/+11
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-162-13/+266
| | | | | | | | | | | | | | This also expands the FPGA interchange Arch BBA to include placement constraints, but doesn't implement them yet. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Remove isValidBelForCellgatecat2021-02-162-14/+0
|/ | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Move CMake logic into fpga-interchange-schema.Keith Rothman2021-02-151-13/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Small fixes from review.Keith Rothman2021-02-151-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add FPGA interchange frontend and backend.Keith Rothman2021-02-156-4/+914
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-151-0/+3
|\ | | | | Support for cell pin to bel pin mappings
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
* | Run "make clangformat".Keith Rothman2021-02-124-66/+53
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Remove capnp and libz for XDC parser PR.Keith Rothman2021-02-121-4/+0
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Refactor XDC parser into a little class for testing purposes.Keith Rothman2021-02-123-14/+52
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Add unknown handles to convert [0] to "[0]".Keith Rothman2021-02-121-0/+11
| | | | | | | | | | | | | | | | Tcl reads something like "set port [get_ports x[0]]" as "invoke proc 0 with zero arguments", rather than just "[0]". To prevent exposing non-Tcl users this, "[<number>]" just return themselves. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Add FPGA interchange XDC parser.Keith Rothman2021-02-125-3/+204
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-2/+1
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* interchange: Base on ArchAPID. Shah2021-02-082-106/+135
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Add RelSlice::ssize and use it when comparing with signed ints.Keith Rothman2021-02-052-27/+28
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Move all string data into BBA file.Keith Rothman2021-02-054-48901/+15
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use RelSlice instead of RelPtr in cases where sizes are present.Keith Rothman2021-02-042-97/+67
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update APIs to conform to style guide.Keith Rothman2021-02-045-67/+48939
| | | | | | | - Change non-Arch methods to snake_case - Adds some utility functions to for accessing bel_data. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove unused method getReservedWireNet.Keith Rothman2021-02-041-7/+0
| | | | | | This was a holdover from the nextpnr-xilinx arch. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update copywrite headers.Keith Rothman2021-02-046-4/+10
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Correct some typos.Keith Rothman2021-02-041-4/+4
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix warnings with signed/unsigned.Keith Rothman2021-02-041-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix fpga_interchange/README.md duplicate patch statement.Keith Rothman2021-02-041-8/+0
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix URLs in Markdown.Keith Rothman2021-02-041-2/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add empty constids.inc for build.Keith Rothman2021-02-041-0/+0
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat".Keith Rothman2021-02-044-148/+100
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add README about initial state of FPGA interchange implementation.Keith Rothman2021-02-041-0/+170
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update FPGA interchange to use IdStringList.Keith Rothman2021-02-042-132/+137
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Start adding data for placement constraint solving.Keith Rothman2021-02-042-50/+43
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Debug BEL bucket data.Keith Rothman2021-02-041-11/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial updates to FPGA interchange arch for BEL buckets.Keith Rothman2021-02-045-0/+247
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Address review comments.Keith Rothman2021-02-043-95/+6
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix BBA import bugs.Keith Rothman2021-02-042-69/+201
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Assorted fixes to new FPGA interchange based arch.Keith Rothman2021-02-043-5/+13
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial compiling version.Keith Rothman2021-02-042-16/+25
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial FPGA interchange (which is just a cut-down xilinx arch).Keith Rothman2021-02-049-0/+2102
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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