| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #743 from YosysHQ/gatecat/site-rsv-ports | gatecat | 2021-07-01 | 5 | -0/+69 |
| |\ | | | | | interchange: Reserve site ports only reachable from dedicated routing | ||||
| | * | interchange: Reserve site ports only reachable from dedicated routing | gatecat | 2021-07-01 | 5 | -0/+69 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | interchange: phys: do not output nets which have no users | Alessandro Comodi | 2021-07-01 | 1 | -1/+12 |
| |/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: fix dedicated interconnect exploration | Alessandro Comodi | 2021-06-30 | 1 | -8/+14 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: Fix dedicated interconnect check when site is the same | gatecat | 2021-06-30 | 1 | -1/+4 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Place IO macro content based on routing | gatecat | 2021-06-30 | 1 | -0/+79 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Track the macros that cells have been expanded from | gatecat | 2021-06-29 | 3 | -0/+8 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #736 from YosysHQ/gatecat/pp-multi-output | gatecat | 2021-06-28 | 1 | -13/+2 |
| |\ | | | | | interchange: Allow site wires driven by more than one bel | ||||
| | * | interchange: Allow site wires driven by more than one bel | gatecat | 2021-06-28 | 1 | -13/+2 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | interchange: Handle disconnected bel pins in dedicated interconnect | gatecat | 2021-06-28 | 1 | -1/+1 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: arch: move macro expansion step before ios packing | Alessandro Comodi | 2021-06-18 | 1 | -1/+1 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Merge pull request #728 from YosysHQ/gatecat/nexus-ram | gatecat | 2021-06-15 | 6 | -0/+382 |
| |\ | | | | | interchange/nexus: Add RAM techmap rule and a RAM test | ||||
| | * | nexus: Add modified version of RAM test | gatecat | 2021-06-15 | 5 | -0/+206 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | nexus: Add PDPSC16K->PDPSC16K_MODE to remap rules | gatecat | 2021-06-15 | 1 | -0/+176 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | interchange: fix phys net writer | Alessandro Comodi | 2021-06-15 | 1 | -5/+2 |
| |/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: Cope with undriven nets in more places | gatecat | 2021-06-14 | 3 | -5/+9 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Fixing old emails and names in copyrights | gatecat | 2021-06-12 | 7 | -9/+9 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: clusters: always get cell bel map and add asserts | Alessandro Comodi | 2021-06-11 | 1 | -23/+13 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: run clang formatter | Alessandro Comodi | 2021-06-11 | 2 | -22/+18 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: clusters: adjust comments | Alessandro Comodi | 2021-06-11 | 2 | -11/+16 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: increase chipinfo version | Alessandro Comodi | 2021-06-11 | 1 | -1/+1 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: tests: counter: emit carries for xc7 | Alessandro Comodi | 2021-06-11 | 2 | -4/+6 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: add support for generating BEL clusters | Alessandro Comodi | 2021-06-11 | 9 | -24/+713 |
| | | | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | fpga_interchange: Add site router tests | Tomasz Michalak | 2021-06-11 | 1 | -0/+3 |
| | | | | | Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com> | ||||
| * | Remove redundant code after hashlib move | gatecat | 2021-06-02 | 1 | -65/+0 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Use hashlib in most remaining code | gatecat | 2021-06-02 | 1 | -2/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Using hashlib in arches | gatecat | 2021-06-02 | 25 | -326/+176 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Use hashlib for core netlist structures | gatecat | 2021-06-02 | 5 | -12/+14 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Add hash() member functions | gatecat | 2021-06-02 | 1 | -0/+5 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add LIFCL-40 EVN tests | gatecat | 2021-06-01 | 10 | -1/+82 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add macro parameter mapping | gatecat | 2021-05-21 | 2 | -3/+53 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Don't error out on missing cell ports | gatecat | 2021-05-21 | 2 | -2/+3 |
| | | | | | | | | This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add LUTRAM test | gatecat | 2021-05-21 | 6 | -0/+169 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Preliminary implementation of macro expansion | gatecat | 2021-05-21 | 3 | -0/+116 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add macro param map rules to chipdb | gatecat | 2021-05-21 | 1 | -0/+24 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add macro data to chipdb | gatecat | 2021-05-21 | 1 | -1/+51 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: phys: add site instance idstr for pseudo tile PIPs | Alessandro Comodi | 2021-05-19 | 1 | -0/+19 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Run clangformat | gatecat | 2021-05-16 | 2 | -5/+7 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: pseudo pips: fix illegal tile pseudo PIPs | Alessandro Comodi | 2021-05-14 | 3 | -21/+62 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: site router: add valid pips list to check during routing | Alessandro Comodi | 2021-05-13 | 3 | -11/+59 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: arch: do not allow site pips within sites | Alessandro Comodi | 2021-05-12 | 1 | -6/+0 |
| | | | | | | | | | | | | | During general routing, the only site pips that can be allowed are those which connect a site wire to the routing interface. This might be too restrictive when dealing with architectures that require more than one site PIPs to route from a driver within a site to the routing interface (which is something that should be allowed in the interchange). Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: Fix bounding box computation | gatecat | 2021-05-11 | 1 | -2/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: site router: fix log messages | Alessandro Comodi | 2021-05-10 | 1 | -3/+3 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: site router: fix illegal site thru paths | Alessandro Comodi | 2021-05-10 | 2 | -0/+23 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: Adding a basic global buffer placer | gatecat | 2021-05-07 | 3 | -32/+132 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Initial global routing implementation | gatecat | 2021-05-07 | 3 | -0/+222 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add more global cell info | gatecat | 2021-05-07 | 1 | -1/+14 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Add stub cluster API impl for remaining arches | gatecat | 2021-05-06 | 2 | -0/+15 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange/nexus: Add counter example | gatecat | 2021-04-30 | 8 | -3/+61 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Implement getWireType | gatecat | 2021-04-30 | 1 | -1/+18 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
 |
index : iCE40/nextpnr | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |
path: root/fpga_interchange