iCE40/nextpnr - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fixing old emails and names in copyrights	gatecat	2021-06-12	1	-1/+1
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	Use hashlib for core netlist structures	gatecat	2021-06-02	1	-4/+4
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	Add Python bindings for placement tests	gatecat	2021-04-15	1	-0/+5
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	Remove isValidBelForCell	gatecat	2021-02-16	1	-3/+0
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
*	Update copywrite headers.	Keith Rothman	2021-02-04	1	-0/+1
\| \| \| \|	Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
*	Add initial updates to FPGA interchange arch for BEL buckets.	Keith Rothman	2021-02-04	1	-0/+2
\| \| \| \|	Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
*	Initial FPGA interchange (which is just a cut-down xilinx arch).	Keith Rothman	2021-02-04	1	-0/+74
	Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>