aboutsummaryrefslogtreecommitdiffstats
path: root/ecp5
Commit message (Collapse)AuthorAgeFilesLines
...
* docs: Tidy upDavid Shah2020-10-011-30/+28
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Update primitives.mdkittennbfive2020-09-301-34/+33
|
* ecp5: Add support for setting PIO clampDavid Shah2020-09-261-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix MESSAGE indicating where externally-built .bbas live.William D. Jones2020-08-221-1/+1
|
* Merge pull request #489 from YosysHQ/dave/ecp5-fix-ioddrx2David Shah2020-08-131-8/+8
|\ | | | | ecp5: Fix how ODDRX2 SCLK/RST are set
| * ecp5: Fix how ODDRX2 SCLK/RST are setDavid Shah2020-08-131-8/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Run fixupHierarchy after packingDavid Shah2020-08-121-0/+1
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Initial conversion to pybind11Miodrag Milanovic2020-07-231-18/+16
|
* ecp5: Add a warning for unknown LPF IOBUF attrsDavid Shah2020-07-131-0/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add SYSCONFIG settings to bitstreamDavid Shah2020-07-124-3/+38
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add parsing of SYSCONFIG line in LPFDavid Shah2020-07-121-1/+20
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #463 from YosysHQ/fix-archcheckDavid Shah2020-07-021-2/+3
|\ | | | | Fix arch checks, and add these to CI
| * ecp5: Fix getTileBelDimZDavid Shah2020-06-291-2/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | CMake: improve logic for discovering Trellis.whitequark2020-07-011-1/+25
| |
* | CMake: fix path checks in chipdb build scripts.whitequark2020-07-011-2/+2
| | | | | | | | | | | | | | `if(NOT DEFINED)` is not appropriate since a variable that contains `-NOTFOUND` still counts as `DEFINED`. This can cause issues if configuration fails, writes `-NOTFOUND` to the cache, and is then restarted.
* | ecp5: Fix derivation of OSCG timing constraintDavid Shah2020-06-291-1/+5
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix clangformat and execute itMiodrag Milanovic2020-06-271-12/+8
|
* Update git ignore locationsMiodrag Milanovic2020-06-271-1/+1
|
* Merge pull request #460 from whitequark/better-embedDavid Shah2020-06-268-109/+66
|\ | | | | Simplify and improve chipdb embedding/loading
| * Simplify and improve chipdb embedding/loading.whitequark2020-06-268-109/+66
| |
* | Fix typowhitequark2020-06-251-1/+1
|/
* CMake: require at least version 3.5 (Ubuntu 16.04).whitequark2020-06-251-1/+1
|
* CMake: rewrite chipdb handling from ground up.whitequark2020-06-256-119/+151
|
* ecp5: Fix placement of DCCs to guarantee routeabilityDavid Shah2020-06-101-2/+44
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #447 from whitequark/wasiDavid Shah2020-05-242-8/+18
|\ | | | | Port nextpnr-{ice40,ecp5} to WASI
| * Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-232-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This involves very few changes, all typical to WASM ports: * WASM doesn't currently support threads or atomics so those are disabled. * WASM doesn't currently support exceptions so the exception machinery is stubbed out. * WASM doesn't (and can't) have mmap(), so an emulation library is used. That library currently doesn't support MAP_SHARED flags, so MAP_PRIVATE is used instead. There is also an update to bring ECP5 bbasm CMake rules to parity with iCE40 ones, since although it is possible to embed chipdb into nextpnr on WASM, a 200 MB WASM file has very few practical uses. The README is not updated and there is no included toolchain file because at the moment it's not possible to build nextpnr with upstream boost and wasi-libc. Boost requires a patch (merged, will be available in boost 1.74.0), wasi-libc requires a few unmerged patches.
* | Merge pull request #440 from YosysHQ/lattice-fixesDavid Shah2020-05-183-0/+28
|\ \ | | | | | | Fixes for the Lattice SERDES eye demo designs
| * | ecp5: Disconnect dedicated DCU inputs if connected to constantsDavid Shah2020-05-141-0/+12
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Improve global routing robustnessDavid Shah2020-05-141-0/+11
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Don't promote VCC/GND to globals even if connected to clock portDavid Shah2020-05-141-0/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | lpf: Support // commentsDavid Shah2020-05-141-0/+3
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | clangformatDavid Shah2020-05-161-1/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #442 from nategraff-sifive/fix-unsupported-spellingDavid Shah2020-05-141-5/+5
|\ \ | |/ |/| Fix spelling of 'unsupported'
| * Fix spelling of 'unsupported'Nathaniel Graff2020-05-131-5/+5
| | | | | | | | Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
* | ecp5: Allow setting drive strength for LVCMOS33D IOsMike Walters2020-05-121-0/+19
|/
* ecp5: MULT18X18D timing fixesDavid Shah2020-05-011-10/+26
| | | | Signed-off-by: David Shah <dave@ds0.me>
* No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
|
* Further condenseRoss Schlaikjer2020-04-291-11/+10
|
* Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
|
* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-293-40/+46
|
* Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
|
* Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
|
* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-283-2/+43
| | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing.
* ecp5: Fix CSDECODE bitgenDavid Shah2020-04-151-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Use dedicated routing for ECLKs where possibleDavid Shah2020-04-141-1/+80
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add TRELLIS_PROGRAM_PREFIXMiodrag Milanovic2020-04-111-4/+6
|
* ecp5: Fix routing bitgen for non-SERDES 'VCIB' tilesDavid Shah2020-04-101-3/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as inputDavid Shah2020-04-091-9/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-073-4/+33
|\ | | | | Add support for REGMODE to DP16KD
| * No need to fetch contextRoss Schlaikjer2020-04-071-3/+2
| |
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-28 02:18:59 +0000