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* | Fix according to comments on PRMiodrag Milanovic2019-02-101-1/+1
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* | Load chipdb from filesystem as optionMiodrag Milanovic2019-02-093-65/+93
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* Merge branch 'ecp5func'David Shah2019-02-084-1/+156
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| * ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGGDavid Shah2019-02-084-1/+156
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #210 from twam/masterDavid Shah2019-01-271-3/+3
|\ \ | |/ |/| Search for trellis in /usr/local/share/trellis if not specified with …
| * Search for trellis in /usr/local/share/trellis if not specified with ↵Tobias Müller2019-01-131-3/+3
| | | | | | | | -DTRELLIS_ROOT
* | Make cross compile possible for mingwMiodrag Milanovic2019-01-271-1/+1
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* ecp5: Add PULLMODE supportDavid Shah2019-01-071-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Check for incorrect use of TRELLIS_IO 'B' pinDavid Shah2018-12-251-0/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix tristate IO insertionDavid Shah2018-12-221-1/+1
| | | | | | Fixes #191 Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fix ODDR when used with manually instantiated TRELLIS_IODavid Shah2018-12-191-0/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fix IOLOGIC ports at the same constant valueDavid Shah2018-12-151-2/+12
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Add IOLOGIC timing and bitstream; ODDR workingDavid Shah2018-12-144-24/+71
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add ODDR packingDavid Shah2018-12-142-1/+25
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding IOLOGIC packingDavid Shah2018-12-142-11/+109
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add {S}IOLOGIC constids and cellDavid Shah2018-12-122-0/+86
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #159 from YosysHQ/ecp5_pllplaceDavid Shah2018-12-012-2/+59
|\ | | | | ecp5: Pre-place PLLs and use dedicated routes into globals
| * ecp5: Pre-place PLLs and use dedicated routes into globalsDavid Shah2018-11-302-2/+59
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+2
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix UR PLL tile coordinatesDavid Shah2018-11-261-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #143 from daveshah1/ecp5_muxesDavid Shah2018-11-265-6/+169
|\ | | | | ecp5: Adding support for LUT extension muxes up to LUT7
| * ecp5: Add support for LUT7 muxDavid Shah2018-11-181-6/+116
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: More optimal LUT6 placementDavid Shah2018-11-163-1/+11
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Adding mux support up to LUT6David Shah2018-11-163-6/+49
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | python: Fixes to get net wires map workingDavid Shah2018-11-221-2/+24
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add 10% safety margin to pip delaysDavid Shah2018-11-161-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: clangformat timing changesDavid Shah2018-11-163-17/+18
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Use speed-grade-specific delay estimateDavid Shah2018-11-161-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix db import, improve timing data debuggingDavid Shah2018-11-163-4/+40
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Allow selection of device speed gradeDavid Shah2018-11-161-3/+26
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Post-rebase fixDavid Shah2018-11-161-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Consider fanout when calculating pip delaysDavid Shah2018-11-161-2/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix timing pip classesDavid Shah2018-11-161-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Use new timing dataDavid Shah2018-11-164-94/+82
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix timing data importDavid Shah2018-11-161-5/+16
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding real timing data to databaseDavid Shah2018-11-166-49/+202
| | | | Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2018-11-162-172/+342
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #119 from cr1901/win-fixDavid Shah2018-11-164-2/+6
|\ | | | | nextpnr-ecp5 Windows Fixes
| * Use native PATH environment-variable separator on Windows for PYTHONPATH. ↵William D. Jones2018-11-031-0/+4
| | | | | | | | | | | | Fixes 'Bad address' error in cmake. Signed-off-by: William D. Jones <thor0505@comcast.net>
| * Rename io.{h,cc} to pio.{h,cc} to avoid naming conflict with ↵William D. Jones2018-11-033-2/+2
| | | | | | | | | | | | Windows-provided io.h. Signed-off-by: William D. Jones <thor0505@comcast.net>
* | ecp5: Better use of BoostDavid Shah2018-11-161-3/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Regression fix & formatDavid Shah2018-11-152-4/+14
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Support LOC attribute on DCUsDavid Shah2018-11-151-1/+25
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Add DCU availability checkDavid Shah2018-11-151-0/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Add timing info for SERDESDavid Shah2018-11-151-1/+26
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: DCU clocking fixesDavid Shah2018-11-151-2/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: EXTREFB fixesDavid Shah2018-11-152-1/+5
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: clangformatDavid Shah2018-11-152-18/+23
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Trim IO connected to top level portsDavid Shah2018-11-151-15/+73
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Adding ancillary DCU belsDavid Shah2018-11-154-1/+57
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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