Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Merge pull request #489 from YosysHQ/dave/ecp5-fix-ioddrx2 | David Shah | 2020-08-13 | 1 | -8/+8 |
|\ | | | | | ecp5: Fix how ODDRX2 SCLK/RST are set | ||||
| * | ecp5: Fix how ODDRX2 SCLK/RST are set | David Shah | 2020-08-13 | 1 | -8/+8 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | ecp5: Run fixupHierarchy after packing | David Shah | 2020-08-12 | 1 | -0/+1 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Initial conversion to pybind11 | Miodrag Milanovic | 2020-07-23 | 1 | -18/+16 |
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* | ecp5: Add a warning for unknown LPF IOBUF attrs | David Shah | 2020-07-13 | 1 | -0/+8 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add SYSCONFIG settings to bitstream | David Shah | 2020-07-12 | 4 | -3/+38 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add parsing of SYSCONFIG line in LPF | David Shah | 2020-07-12 | 1 | -1/+20 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #463 from YosysHQ/fix-archcheck | David Shah | 2020-07-02 | 1 | -2/+3 |
|\ | | | | | Fix arch checks, and add these to CI | ||||
| * | ecp5: Fix getTileBelDimZ | David Shah | 2020-06-29 | 1 | -2/+3 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | CMake: improve logic for discovering Trellis. | whitequark | 2020-07-01 | 1 | -1/+25 |
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* | | CMake: fix path checks in chipdb build scripts. | whitequark | 2020-07-01 | 1 | -2/+2 |
| | | | | | | | | | | | | | | `if(NOT DEFINED)` is not appropriate since a variable that contains `-NOTFOUND` still counts as `DEFINED`. This can cause issues if configuration fails, writes `-NOTFOUND` to the cache, and is then restarted. | ||||
* | | ecp5: Fix derivation of OSCG timing constraint | David Shah | 2020-06-29 | 1 | -1/+5 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Fix clangformat and execute it | Miodrag Milanovic | 2020-06-27 | 1 | -12/+8 |
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* | Update git ignore locations | Miodrag Milanovic | 2020-06-27 | 1 | -1/+1 |
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* | Merge pull request #460 from whitequark/better-embed | David Shah | 2020-06-26 | 8 | -109/+66 |
|\ | | | | | Simplify and improve chipdb embedding/loading | ||||
| * | Simplify and improve chipdb embedding/loading. | whitequark | 2020-06-26 | 8 | -109/+66 |
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* | | Fix typo | whitequark | 2020-06-25 | 1 | -1/+1 |
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* | CMake: require at least version 3.5 (Ubuntu 16.04). | whitequark | 2020-06-25 | 1 | -1/+1 |
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* | CMake: rewrite chipdb handling from ground up. | whitequark | 2020-06-25 | 6 | -119/+151 |
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* | ecp5: Fix placement of DCCs to guarantee routeability | David Shah | 2020-06-10 | 1 | -2/+44 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #447 from whitequark/wasi | David Shah | 2020-05-24 | 2 | -8/+18 |
|\ | | | | | Port nextpnr-{ice40,ecp5} to WASI | ||||
| * | Port nextpnr-{ice40,ecp5} to WASI. | whitequark | 2020-05-23 | 2 | -8/+18 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This involves very few changes, all typical to WASM ports: * WASM doesn't currently support threads or atomics so those are disabled. * WASM doesn't currently support exceptions so the exception machinery is stubbed out. * WASM doesn't (and can't) have mmap(), so an emulation library is used. That library currently doesn't support MAP_SHARED flags, so MAP_PRIVATE is used instead. There is also an update to bring ECP5 bbasm CMake rules to parity with iCE40 ones, since although it is possible to embed chipdb into nextpnr on WASM, a 200 MB WASM file has very few practical uses. The README is not updated and there is no included toolchain file because at the moment it's not possible to build nextpnr with upstream boost and wasi-libc. Boost requires a patch (merged, will be available in boost 1.74.0), wasi-libc requires a few unmerged patches. | ||||
* | | Merge pull request #440 from YosysHQ/lattice-fixes | David Shah | 2020-05-18 | 3 | -0/+28 |
|\ \ | | | | | | | Fixes for the Lattice SERDES eye demo designs | ||||
| * | | ecp5: Disconnect dedicated DCU inputs if connected to constants | David Shah | 2020-05-14 | 1 | -0/+12 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | ecp5: Improve global routing robustness | David Shah | 2020-05-14 | 1 | -0/+11 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | ecp5: Don't promote VCC/GND to globals even if connected to clock port | David Shah | 2020-05-14 | 1 | -0/+2 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | lpf: Support // comments | David Shah | 2020-05-14 | 1 | -0/+3 |
| |/ | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | clangformat | David Shah | 2020-05-16 | 1 | -1/+2 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Merge pull request #442 from nategraff-sifive/fix-unsupported-spelling | David Shah | 2020-05-14 | 1 | -5/+5 |
|\ \ | |/ |/| | Fix spelling of 'unsupported' | ||||
| * | Fix spelling of 'unsupported' | Nathaniel Graff | 2020-05-13 | 1 | -5/+5 |
| | | | | | | | | Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> | ||||
* | | ecp5: Allow setting drive strength for LVCMOS33D IOs | Mike Walters | 2020-05-12 | 1 | -0/+19 |
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* | ecp5: MULT18X18D timing fixes | David Shah | 2020-05-01 | 1 | -10/+26 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | No cell delay for clocked MULT18X18D | Ross Schlaikjer | 2020-04-30 | 1 | -0/+2 |
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* | Further condense | Ross Schlaikjer | 2020-04-29 | 1 | -11/+10 |
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* | Dedupe clock error check | Ross Schlaikjer | 2020-04-29 | 1 | -12/+13 |
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* | Issue warning for mixed-mode inputs | Ross Schlaikjer | 2020-04-29 | 3 | -40/+46 |
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* | Handle register timing case | Ross Schlaikjer | 2020-04-29 | 1 | -6/+58 |
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* | Use registered port class on mult18x18 | Ross Schlaikjer | 2020-04-29 | 1 | -3/+5 |
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* | Alter MULT18X18D timing db based on register config | Ross Schlaikjer | 2020-04-28 | 3 | -2/+43 |
| | | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing. | ||||
* | ecp5: Fix CSDECODE bitgen | David Shah | 2020-04-15 | 1 | -0/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Use dedicated routing for ECLKs where possible | David Shah | 2020-04-14 | 1 | -1/+80 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Add TRELLIS_PROGRAM_PREFIX | Miodrag Milanovic | 2020-04-11 | 1 | -4/+6 |
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* | ecp5: Fix routing bitgen for non-SERDES 'VCIB' tiles | David Shah | 2020-04-10 | 1 | -3/+12 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as input | David Shah | 2020-04-09 | 1 | -9/+7 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-database | David Shah | 2020-04-07 | 3 | -4/+33 |
|\ | | | | | Add support for REGMODE to DP16KD | ||||
| * | No need to fetch context | Ross Schlaikjer | 2020-04-07 | 1 | -3/+2 |
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| * | Change assert to error | Ross Schlaikjer | 2020-04-07 | 1 | -2/+5 |
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| * | Rearrange bool algebra | Ross Schlaikjer | 2020-04-07 | 1 | -2/+2 |
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| * | Actually just move all the logic to ArchInfo | Ross Schlaikjer | 2020-04-07 | 3 | -19/+23 |
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| * | Extract regmode configuration to ArchInfo | Ross Schlaikjer | 2020-04-07 | 3 | -8/+16 |
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