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* Further condenseRoss Schlaikjer2020-04-291-11/+10
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* Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
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* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-291-13/+34
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* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-281-0/+35
| | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing.
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-071-0/+23
|\ | | | | Add support for REGMODE to DP16KD
| * No need to fetch contextRoss Schlaikjer2020-04-071-3/+2
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| * Change assert to errorRoss Schlaikjer2020-04-071-2/+5
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| * Rearrange bool algebraRoss Schlaikjer2020-04-071-2/+2
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| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-071-2/+13
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| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-071-0/+10
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* | ecp5: Allow use of IDDRXN and ODDRXN type primitives on the same pinDavid Shah2020-04-031-0/+10
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix tieoff of unused DELAY signalsDavid Shah2020-01-211-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for flipflops with preloadDavid Shah2019-12-071-2/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix placement of DDRDLLADavid Shah2019-11-291-0/+26
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Improve flipflop packing densityDavid Shah2019-11-201-0/+153
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix handling of custom DEL_VALUEDavid Shah2019-11-181-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add logic utilisation before packing statisticsDavid Shah2019-11-181-0/+45
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #345 from YosysHQ/dave/sdfDavid Shah2019-11-181-11/+3
|\ | | | | Improve handling of top level IO and add SDF support
| * ecp5: Preserve top level IO properlyDavid Shah2019-10-181-11/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Copy timing constraints across ECLKBRIDGECSDavid Shah2019-11-011-1/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Fix placement of ECLKBRIDGECSDavid Shah2019-11-011-11/+41
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for ECLKBRIDGECSDavid Shah2019-10-111-1/+52
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix tristate IO registersDavid Shah2019-10-091-3/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for IO registersDavid Shah2019-10-091-0/+97
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add IDDR71B supportDavid Shah2019-10-091-3/+15
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add ODDR71B supportDavid Shah2019-10-091-3/+14
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix parametersDavid Shah2019-10-041-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding support for 36-bit wide PDP RAMsDavid Shah2019-10-011-0/+53
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Move clock constraints across IO and DCCADavid Shah2019-09-131-0/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add GSR/SGSR supportDavid Shah2019-08-271-0/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add --out-of-context for building hard macrosDavid Shah2019-08-071-1/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add a check for legacy parameter valuesDavid Shah2019-08-061-0/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: New Property interfaceDavid Shah2019-08-051-62/+66
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix missing LUT inputs, fixes #301David Shah2019-07-101-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Use flags for each stepMiodrag Milanovic2019-06-141-1/+1
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* Save top level attrs and store current stepMiodrag Milanovic2019-06-071-0/+1
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* ecp5: Use an attribute to store is_globalDavid Shah2019-06-071-2/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* WIP saving/loading attributesMiodrag Milanovic2019-06-071-0/+1
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* Added support for attributes/properties typesMiodrag Milanovic2019-06-011-1/+1
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* ecp5: Fix USRMCLK primitiveDavid Shah2019-05-101-0/+14
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: DELAY fixesDavid Shah2019-02-251-11/+10
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Improve packing densityDavid Shah2019-02-251-0/+58
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add criticality-based LUT permutationDavid Shah2019-02-251-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Speed up timing analysisDavid Shah2019-02-251-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: DELAYF/G fixesDavid Shah2019-02-241-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Connect unused DQSBUF inputs to GNDDavid Shah2019-02-241-14/+30
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Compute derived constraints iterativelyDavid Shah2019-02-241-52/+79
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Derived constraint support for PLLs, clock dividers and oscillatorsDavid Shah2019-02-241-0/+115
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fixes for litedramDavid Shah2019-02-241-0/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Add DELAYF/DELAYG supportDavid Shah2019-02-241-1/+122
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
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