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* clangformatgatecat2021-04-301-40/+30
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add check_alu to Ecp5PackerAdam Greig2021-04-291-15/+123
| | | | | | | | | | | Checks that every ALU54B is correctly connected to two MULT18X18Ds: * SIGNEDIA and SIGNEDIB connected to SIGNEDP * MA and MB connected to P * A and B connected to {ROA, ROB} Diamond enforces these requirements; the connections are fixed in any event so no other connection is possible.
* Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-291-0/+24
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* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-17/+17
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use snake case for arch-specific functionsD. Shah2021-02-031-6/+7
| | | | | | | This makes the difference clearer between the general arch API that everyone must implement; and helper functions specific to one arch. Signed-off-by: D. Shah <dave@ds0.me>
* refactor: Replace getXName().c_str(ctx) with ctx->nameOfXD. Shah2021-02-021-1/+1
| | | | | | This makes the ongoing migration to IdStringList easier. Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Proof-of-concept using IdStringList for bel namesD. Shah2021-02-021-25/+21
| | | | | | | | | | | This uses the new IdStringList API to store bel names for the ECP5. Note that other arches and the GUI do not yet build with this proof-of-concept patch. getBelByName still uses the old implementation and could be more efficiently implemented with further development. Signed-off-by: D. Shah <dave@ds0.me>
* cleanup: Spelling fixesD. Shah2021-01-281-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Fix some tricky ECLKSYNCB/CLKDIVF packing casesDavid Shah2020-10-091-0/+64
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #489 from YosysHQ/dave/ecp5-fix-ioddrx2David Shah2020-08-131-8/+8
|\ | | | | ecp5: Fix how ODDRX2 SCLK/RST are set
| * ecp5: Fix how ODDRX2 SCLK/RST are setDavid Shah2020-08-131-8/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Run fixupHierarchy after packingDavid Shah2020-08-121-0/+1
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix derivation of OSCG timing constraintDavid Shah2020-06-291-1/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Disconnect dedicated DCU inputs if connected to constantsDavid Shah2020-05-141-0/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Further condenseRoss Schlaikjer2020-04-291-11/+10
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* Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
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* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-291-13/+34
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* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-281-0/+35
| | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing.
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-071-0/+23
|\ | | | | Add support for REGMODE to DP16KD
| * No need to fetch contextRoss Schlaikjer2020-04-071-3/+2
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| * Change assert to errorRoss Schlaikjer2020-04-071-2/+5
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| * Rearrange bool algebraRoss Schlaikjer2020-04-071-2/+2
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| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-071-2/+13
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| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-071-0/+10
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* | ecp5: Allow use of IDDRXN and ODDRXN type primitives on the same pinDavid Shah2020-04-031-0/+10
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix tieoff of unused DELAY signalsDavid Shah2020-01-211-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for flipflops with preloadDavid Shah2019-12-071-2/+6
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix placement of DDRDLLADavid Shah2019-11-291-0/+26
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Improve flipflop packing densityDavid Shah2019-11-201-0/+153
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix handling of custom DEL_VALUEDavid Shah2019-11-181-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add logic utilisation before packing statisticsDavid Shah2019-11-181-0/+45
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #345 from YosysHQ/dave/sdfDavid Shah2019-11-181-11/+3
|\ | | | | Improve handling of top level IO and add SDF support
| * ecp5: Preserve top level IO properlyDavid Shah2019-10-181-11/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Copy timing constraints across ECLKBRIDGECSDavid Shah2019-11-011-1/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ecp5: Fix placement of ECLKBRIDGECSDavid Shah2019-11-011-11/+41
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for ECLKBRIDGECSDavid Shah2019-10-111-1/+52
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix tristate IO registersDavid Shah2019-10-091-3/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for IO registersDavid Shah2019-10-091-0/+97
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add IDDR71B supportDavid Shah2019-10-091-3/+15
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add ODDR71B supportDavid Shah2019-10-091-3/+14
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix parametersDavid Shah2019-10-041-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding support for 36-bit wide PDP RAMsDavid Shah2019-10-011-0/+53
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Move clock constraints across IO and DCCADavid Shah2019-09-131-0/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add GSR/SGSR supportDavid Shah2019-08-271-0/+11
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add --out-of-context for building hard macrosDavid Shah2019-08-071-1/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add a check for legacy parameter valuesDavid Shah2019-08-061-0/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: New Property interfaceDavid Shah2019-08-051-62/+66
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix missing LUT inputs, fixes #301David Shah2019-07-101-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Use flags for each stepMiodrag Milanovic2019-06-141-1/+1
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* Save top level attrs and store current stepMiodrag Milanovic2019-06-071-0/+1
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