aboutsummaryrefslogtreecommitdiffstats
path: root/ecp5/arch.h
Commit message (Collapse)AuthorAgeFilesLines
* Add missing <set> includesgatecat2023-01-201-3/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add remapping of DSP clk/ce/rst signals in a block.Adam Greig2023-01-041-0/+6
| | | | | | | | | | | | | | | | | | Each DSP block contains two slices, and each slice contains multiple MULT18X18D and ALU54B units. Each unit configures each register to use any of CLK0/1/2/3, CE0/1/2/3, and RST0/1/2/3 ports, and the ports are connected per unit (so for example, two MULTs in the same block could connect their CLK0s to different external signals). However, the hardware only has one actual port per block, so it's required that all CLK0 signals within a block are the same. Because the packer is in general allowed to combine two unrelated units into one block, it may end up combining units that use different signals for the same port, which would eventually have caused a router failure. This commit adds validity checks which ensure only unique signals are used per block, and adds remapping so that conflicting signals are automatically reassigned when possible and required.
* api: add explain_invalid option to isBelLocationValidgatecat2022-12-071-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-071-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-021-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use IdString::in instead of || chainsgatecat2022-08-101-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-071-25/+82
|
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-1/+1
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: LUT permutation supportgatecat2021-12-131-2/+48
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Reduce some chipdb fields sizesMatt Johnston2021-12-131-6/+5
| | | | This reduces the final binary size by ~7 MB for 85k
* clangformatgatecat2021-12-121-4/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use a vector rather than dictMatt Johnston2021-12-121-14/+83
| | | | | This improves router1 performance vs the default dict Using it for wire2net, pip2net, wire_fanout
* Fixing old emails and names in copyrightsgatecat2021-06-121-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-20/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-5/+8
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-24/+11
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-161-1/+0
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-16/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-081-226/+113
|\ | | | | Create a new BaseArch that formally specifies the Arch API and provides some base implementations
| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| | | | | | | | | | | | | | Arches might otherwise have range types named ambigiously with the entry in ArchRanges. Signed-off-by: D. Shah <dave@ds0.me>
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-051-4/+4
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Add default implementation of bel bucket functionsD. Shah2021-02-051-41/+2
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Add default implementation of some range-returning functionsD. Shah2021-02-051-12/+0
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Add a few more functions to ArchBaseD. Shah2021-02-051-3/+4
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * ecp5: Use common wire/pip bindingD. Shah2021-02-051-82/+6
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * nextpnr: Use templates to specify range typesD. Shah2021-02-051-18/+46
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * nextpnr: Add base virtual functions for non-range Arch APID. Shah2021-02-051-84/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | This makes the Arch API clearer and also allows a base implementation of functions to reduce the amount of complexity to get a basic Arch up and running. Currently this only implements these for functions that don't return a range. Range-returning functions will require more work in order due to the current 'duck typing' approach (probably a struct that contains the range types combined with templating.) Signed-off-by: D. Shah <dave@ds0.me>
* | Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-081-4/+4
|/ | | | Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Use snake case for arch-specific functionsD. Shah2021-02-031-62/+62
| | | | | | | This makes the difference clearer between the general arch API that everyone must implement; and helper functions specific to one arch. Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Implement IdStringList for all arch object namesD. Shah2021-02-021-14/+12
| | | | | | | This is a complete implementation of IdStringList for ECP5; excluding the GUI (which you will have to disable for it to build). Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Proof-of-concept using IdStringList for bel namesD. Shah2021-02-021-5/+8
| | | | | | | | | | | This uses the new IdStringList API to store bel names for the ECP5. Note that other arches and the GUI do not yet build with this proof-of-concept patch. getBelByName still uses the old implementation and could be more efficiently implemented with further development. Signed-off-by: D. Shah <dave@ds0.me>
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Run "make clangformat".Keith Rothman2021-02-021-18/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Rename Partition -> BelBucket.Keith Rothman2021-02-021-19/+19
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor ECP5 to new Partition API.Keith Rothman2021-02-021-0/+44
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial refactoring of placer API.Keith Rothman2021-02-021-0/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Move RelPtr/RelSlice out of arches into commonD. Shah2021-01-271-37/+1
| | | | | | | The bba approach seems widely used enough that it's reasonable for this to become part of common code. Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Switch from RelPtr to RelSliceD. Shah2021-01-271-61/+62
| | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me>
* RelPtr: remove copy constructor and copy assignmentDavid Shah2020-11-131-0/+3
| | | | | | | These operations are meaningless for a data structure that references another structure relative to its location. Signed-off-by: David Shah <dave@ds0.me>
* Remove wire alias APIDavid Shah2020-10-151-9/+0
| | | | | | It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink. Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Fix getTileBelDimZDavid Shah2020-06-291-2/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Simplify and improve chipdb embedding/loading.whitequark2020-06-261-10/+3
|
* CMake: rewrite chipdb handling from ground up.whitequark2020-06-251-1/+1
|
* ecp5: Proper support for '12k' deviceDavid Shah2020-03-131-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Allow selection of router algorithmDavid Shah2020-02-031-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Router2 test integrationDavid Shah2020-02-031-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into mmicko/ecp5_guiMiodrag Milanovic2019-12-281-1/+7
|\
| * ecp5: Fix 25k DDRDLLA bitstream genDavid Shah2019-11-291-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 14:34:32 +0000