aboutsummaryrefslogtreecommitdiffstats
path: root/common
Commit message (Collapse)AuthorAgeFilesLines
* Fix bug in router2 where router may give up too early.Keith Rothman2021-04-061-1/+13
| | | | | | | | | | Was introduced in #612. The logic before was intended to prevent the router from terminating early when not using a bounding box, but the fix in #612 simply removed that, meaning that the router might terminate early incorrectly. The solution here is to only use the toexplore hysteric once a solution is found. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* interchange: Fix illegal placementsgatecat2021-03-301-1/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-2/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-232-1/+130
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #634 from litghost/add_get_bel_pin_typegatecat2021-03-221-0/+2
|\ | | | | Add getBelPinType to Python interface.
| * Add getBelPinType to Python interface.Keith Rothman2021-03-221-0/+2
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-223-13/+13
|/ | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-191-0/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat". to fix up master.Keith Rothman2021-03-184-4/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Moving hash map/set type selection to header.Keith Rothman2021-03-172-8/+52
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add missing includes to fix WASI build.whitequark2021-03-162-0/+5
|
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-159-23/+29
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #621 from litghost/fix_header_nightmaregatecat2021-03-1530-2395/+3104
|\ | | | | Split nextpnr.h to allow for linear inclusion.
| * Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-1530-2395/+3104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | opt-timing: Skip undriven netsgatecat2021-03-151-0/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add support for partially routed nets from the placer in router2.Keith Rothman2021-03-122-28/+54
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add diagnostic prints to debug lookahead performance.Keith Rothman2021-03-101-13/+41
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Only depend on Abseil in threaded builds.whitequark2021-03-101-0/+6
| | | | | | Abseil has a hard dependency on threads (not just in the build system but in many places in the base libraries), so there is no way to use it on WASI at the moment.
* Merge pull request #607 from litghost/add_absl_flat_hash_mapgatecat2021-03-091-1/+2
|\ | | | | Add absl::flat_hash_map.
| * Add absl::flat_hash_map.Keith Rothman2021-03-011-1/+2
| | | | | | | | | | | | | | This lowers the CPU cost of using the flat wire map in router2, and should use less memory as well. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #609 from YosysHQ/gatecat/sta-v2gatecat2021-03-098-242/+937
|\ \ | | | | | | Use new timing engine for criticality
| * | timing: Integration tweaksgatecat2021-03-054-4/+9
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Skip route delays for unplaced/nullptr cellsgatecat2021-03-041-1/+6
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Replace all users of criticality with new enginegatecat2021-03-044-229/+52
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Use new engine in SA except for budget-based modegatecat2021-03-041-10/+7
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Use new engine for HeAPgatecat2021-03-043-14/+19
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add support for critical path printinggatecat2021-03-042-0/+69
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Slack and criticality computationgatecat2021-03-042-0/+47
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Produce plausible Fmax figuregatecat2021-03-042-1/+12
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add Fmax printing for debugginggatecat2021-03-042-0/+23
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add backwards path walkinggatecat2021-03-043-1/+71
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add forward path walkinggatecat2021-03-042-0/+105
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Compute domain pairsgatecat2021-03-042-13/+59
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add port-domain trackinggatecat2021-03-043-1/+115
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Add topological sort from Yosysgatecat2021-03-043-0/+130
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Import cell delays to our own structuresgatecat2021-03-042-0/+123
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | timing: Data structures for STA rewritegatecat2021-03-041-0/+122
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | router2: Fix vast perf drop when leaving bounding boxgatecat2021-03-081-1/+1
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #604 from litghost/add_counter_testgatecat2021-03-031-0/+2
|\ \ | | | | | | Add counter test for FPGA interchange
| * | Initial LUT rotation logic.Keith Rothman2021-02-261-0/+2
| |/ | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #605 from litghost/add_placement_sanity_checkgatecat2021-03-025-11/+106
|\ \ | |/ |/| Add placement sanity check in placer_heap.
| * Correct spelling of RAII and add missing check in unlock_early.Keith Rothman2021-03-011-10/+19
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use scope in router1/2 and placer1.Keith Rothman2021-03-014-10/+18
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Fix latent bug with context locking in placer HeAP.Keith Rothman2021-02-262-10/+68
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add placement sanity check in placer_heap.Keith Rothman2021-02-261-1/+21
| | | | | | | | | | | | Also check return of placer1_refine. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Prevent trival misplacements in placer1.Keith Rothman2021-02-261-0/+12
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove unused advanced timing constraint APIgatecat2021-02-262-187/+0
| | | | | | | | | | | | | This API was simply an attractive nuisance as no code was ever developed to actually process timing constraints (other than clock constraints which use a different API). While I do want to consider basic false path support, among other things, in the near future; I plan for this to use a new API that doesn't add complexity to the BaseCtx/Context monstrosity and that is easier to use on the timing analysis side. Signed-off-by: gatecat <gatecat@ds0.me>
* Allow router2 to use routed but not fixed arcs.Keith Rothman2021-02-251-4/+54
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix compiler warnings introduced by -Wextragatecat2021-02-253-6/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #591 from litghost/add_constant_networkgatecat2021-02-252-10/+9
|\ | | | | Add constant network support to FPGA interchange arch
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 20:16:25 +0000