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| * Remove some signedness warnings.Keith Rothman2021-02-232-10/+9
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #597 from litghost/add_dynamic_bitarraygatecat2021-02-241-0/+79
|\ \ | | | | | | Add dynamic bitarray to common library.
| * | Fix some bugs found in review.Keith Rothman2021-02-241-5/+2
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Add dynamic bitarray to common library.Keith Rothman2021-02-231-0/+82
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #595 from litghost/const_cell_infogatecat2021-02-231-2/+2
|\ \ \ | | |/ | |/| Change CellInfo in getBelPinsForCellPin to be const.
| * | Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-2/+2
| |/ | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #596 from litghost/make_clang_formatgatecat2021-02-232-11/+16
|\ \ | |/ |/| Run "make clangformat" to fix formatting in new Bits library.
| * Run "make clangformat" to fix new Bits library.Keith Rothman2021-02-232-11/+16
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Refactor some common code to CellInfo methodsgatecat2021-02-236-38/+43
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | HeAP: Document legalise_placement_strict bettergatecat2021-02-231-3/+45
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Demote the 'no clocks' warning to info and make clearergatecat2021-02-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #592 from YosysHQ/gatecat/rework-delaygatecat2021-02-207-35/+98
|\ | | | | Replace DelayInfo with DelayPair and DelayQuad
| * python: Bindings for DelayPair and DelayQuadgatecat2021-02-191-0/+25
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-196-35/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
| * Add DelayPair and DelayQuad structuresgatecat2021-02-191-0/+35
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2021-02-191-1/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #576 from litghost/add_cell_bel_pin_mappinggatecat2021-02-196-0/+443
|\ | | | | Complete FPGA interchange Arch to the point where it can route a wire
| * Use Bits library for bit instrisics.Keith Rothman2021-02-171-2/+4
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Refactor "get only from iterator" to a utility.Keith Rothman2021-02-171-0/+23
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Working on standing up initial constraints system.Keith Rothman2021-02-175-0/+418
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Expose ice40 arch placer-heap internal parameters.Balint Cristian2021-02-182-4/+32
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* Add a Bits utility library.Keith Rothman2021-02-172-0/+124
| | | | | | | This library captures use of __builtin_popcount and __builtin_ctz on GCC/clang and hopefully handles the MSVC case. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove isValidBelForCellgatecat2021-02-164-24/+38
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-155-173/+253
|\ | | | | Support for cell pin to bel pin mappings
| * router2: Support for multiple bel pins per cell pingatecat2021-02-101-85/+95
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * router1: Support for multiple bel pins per cell pingatecat2021-02-101-62/+78
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Start making use of getBelPinsForCellPin APIgatecat2021-02-105-37/+83
| | | | | | | | | | | | | | | | | | | | | | | | This replaces getNetinfoSinkWire with 3 new functions for different use cases. At the moment all existing code has been moved to getNetinfoSinkWire with phys_idx=0 so the build doesn't break; but this won't yet function properly with more than one sink. But it provides a base on which to work on refactoring the routers to support this case. Signed-off-by: gatecat <gatecat@ds0.me>
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #579 from litghost/add_control_for_split_iogatecat2021-02-121-0/+1
|\ \ | | | | | | Add control to whether GenericFrontend splits IO ports.
| * | Add control to whether GenericFrontend splits IO ports.Keith Rothman2021-02-111-0/+1
| |/ | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Make BaseArch getDecalGraphics return an empty rangegatecat2021-02-121-1/+1
| | | | | | | | | | | | | | Fix assertion failure when opening the GUI on an arch without any decals. Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #580 from litghost/add_design_loaded_state_variablegatecat2021-02-122-1/+6
|\ \ | | | | | | Add design_loaded state variable.
| * | Add design_loaded state variable.Keith Rothman2021-02-112-1/+6
| |/ | | | | | | | | | | | | This is to decouple the command line flag "--json" and enable other frontend's. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* / Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-112-3/+8
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove the unused CellInfo::pins fieldgatecat2021-02-103-25/+0
| | | | | | | | | | | No arches ever actually used this to implement a Cell->Bel pin mapping, and in practice if any did try they would inevitably hit bitrot. This field had limited use in practice as it is necessary to also support cases where one cell pin maps to more than one bel pin. Removing this old field is the first step towards developing a new API for this. Signed-off-by: gatecat <gatecat@ds0.me>
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-0/+21
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Make BaseCtx destructor virtualgatecat2021-02-081-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-42/+48
| | | | | | | Arches might otherwise have range types named ambigiously with the entry in ArchRanges. Signed-off-by: D. Shah <dave@ds0.me>
* Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-0/+3
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Switch to BaseArchD. Shah2021-02-051-0/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Add pure-virtual ArchAPI interfaceD. Shah2021-02-051-104/+198
| | | | | | | | | This splits out the pure-virtual definition of the architecture API into ArchAPI; leaving BaseArch to only provide default implementations (which can now be completely opted out of by deriving from ArchAPI instead of BaseArch). Signed-off-by: D. Shah <dave@ds0.me>
* Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-051-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Add default implementation of bel bucket functionsD. Shah2021-02-051-5/+89
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Add default implementation of some range-returning functionsD. Shah2021-02-051-5/+27
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Add a few more functions to ArchBaseD. Shah2021-02-051-8/+14
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* ecp5: Use common wire/pip bindingD. Shah2021-02-051-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Fix now-illegal use of reinterpret_castD. Shah2021-02-051-3/+5
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* nextpnr: Example of shared wire/bel/pip binding codeD. Shah2021-02-051-13/+106
| | | | | | Currently not actually being tested Signed-off-by: D. Shah <dave@ds0.me>
* nextpnr: Use templates to specify range typesD. Shah2021-02-051-0/+21
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* nextpnr: Add base virtual functions for non-range Arch APID. Shah2021-02-051-0/+108
| | | | | | | | | | | | | This makes the Arch API clearer and also allows a base implementation of functions to reduce the amount of complexity to get a basic Arch up and running. Currently this only implements these for functions that don't return a range. Range-returning functions will require more work in order due to the current 'duck typing' approach (probably a struct that contains the range types combined with templating.) Signed-off-by: D. Shah <dave@ds0.me>
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