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* Set the locale as early as possibleYRabbit2022-03-161-1/+9
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* clangformatgatecat2022-03-091-5/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add missing part of commit aee35768.Catherine2022-03-081-1/+4
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* Disable parallel refinement on WebAssembly.Catherine2022-03-052-1/+19
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* parallel_refine: New, parallelised placement refinement passgatecat2022-03-035-2/+1012
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* Switch to potentially-sparse net users arraygatecat2022-02-2714-260/+285
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* Add indexed_store container typegatecat2022-02-262-0/+267
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add IdStringList::concat overrides taking IdStringgatecat2022-02-201-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New member functions to replace design_utilsgatecat2022-02-186-172/+167
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-163-11/+10
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* run clangformatgatecat2022-02-031-3/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Add GUI.YRabbit2022-01-292-0/+4
| | | | | | | | | | | | | | | * Items such as LUT, DFF, MUX, ALU, IOB are displayed; * Local wires, 1-2-4-8 wires are displayed; * The clock spines, taps and branches are displayed with some caveats. For now, you can not create a project in the GUI because of possible conflict with another PR (about GW1NR-9C support), but you can specify the board in the command line and load .JSON and .CST in the GUI. Although ALUs are displayed, but the CIN and COUT wires are not. This is still an unsolved problem. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Switched integer pair hashing function from DJB2 to CantorMaciej Kurc2022-01-111-2/+5
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* SSOArray: Implement move and assignment operatorsgatecat2021-12-301-0/+20
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Refactor for faster performancegatecat2021-12-301-9/+8
| | | | | | | | This won't affect Python-built arches significantly; but will be useful for the future 'viaduct' functionality where generic routing graphs can be built on the C++ side; too. Signed-off-by: gatecat <gatecat@ds0.me>
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-198-11/+34
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* router1: Experimental timing-driven ripup supportgatecat2021-12-183-6/+103
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router1: Improve timing heuristicgatecat2021-12-181-13/+25
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* python: Bind getBelLocation/getPipLocationgatecat2021-12-142-1/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Improve reservation debug logginggatecat2021-12-121-2/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #867 from mkj/mkj/routerspeed2gatecat2021-12-121-2/+1
|\ | | | | Improvements to ecp5 router speed
| * ecp5: Keep "visited" localMatt Johnston2021-12-121-2/+1
| | | | | | | | Otherwise it keeps growing boundless and slows down small arcs
* | router2: Error instead of hang in case of reservation conflictsgatecat2021-12-121-0/+3
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* common: Improved the random seed initialisation for the contextdx-mon2021-11-191-6/+4
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* router2: Disable criticality sorting towards end of routinggatecat2021-10-091-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* hashlib: Support for std::array keysgatecat2021-10-071-0/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix Cygwin buildgatecat2021-10-011-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Code formattingMaciej Kurc2021-09-294-119/+87
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Brought back printout of critical path source file references, added ↵Maciej Kurc2021-09-293-28/+74
| | | | | | clk-to-q, source and setup segment types Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Shifted moving of data containers after printingMaciej Kurc2021-09-281-11/+11
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added a commandline option controlled writeout of per-net timing detailsMaciej Kurc2021-09-284-9/+22
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added description of the JSON report structure.Maciej Kurc2021-09-281-1/+73
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Moved timing result report storage to the context, added its writeout to the ↵Maciej Kurc2021-09-286-282/+279
| | | | | | current utilization and fmax report Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added reporting critical paths in JSON formatMaciej Kurc2021-09-281-25/+49
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Decoupled critical path report generation from its printingMaciej Kurc2021-09-281-134/+264
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Switched to JSON format for timing analysis reportMaciej Kurc2021-09-281-33/+81
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Added writing a CSV report with timing analysis of each net branchMaciej Kurc2021-09-284-6/+89
| | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* idstring: Add 'in' functiongatecat2021-09-271-0/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #812 from antmicro/MacroCellsgatecat2021-09-272-4/+4
|\ | | | | Convert macros to clusters for better placement
| * Fix small isses and code formattingMaciej Dudek2021-09-271-2/+2
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Adding MacroCell placementMaciej Dudek2021-09-231-4/+3
| | | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
| * Adding support for MacroCellsMaciej Dudek2021-09-231-2/+3
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* | router2: Allow overriding resource costsgatecat2021-09-242-2/+9
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #825 from antmicro/chain_swap_fixgatecat2021-09-231-2/+15
|\ | | | | Fix chain swap
| * Fix chain swapMaciej Dudek2021-09-231-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | Issue was due to dest_bels being not cleared between clusters unbindes, causing newly bind bels to be unbinded and having their old bel value changed to new bel value. Then when swap failed 2 cells were being bind to a single bel. I tested leaving dest_bels in the function scope and moving it to the loop scope. Code with dest_bels in the loop scope was faster than leaving it in the function scope, and checking if the cell is in the processed cluster. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | python: Restore SIGINT handler while running a Python scriptgatecat2021-09-221-1/+7
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* placer1: Remove redundant relative constraint checkgatecat2021-09-221-4/+0
| | | | | | Macros with potentially inconsistent spacing are now permissible. Signed-off-by: gatecat <gatecat@ds0.me>
* placer1: Fix cluster swap cost updatesgatecat2021-09-181-8/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* timing: Always use max delay for required timegatecat2021-09-181-3/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* timing: Fix slack for unconstrained clocksgatecat2021-09-181-6/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
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