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* interchange: Bump versionsgatecat2021-05-212-1/+1
* interchange: Add macro parameter mappinggatecat2021-05-212-3/+53
* interchange: Don't error out on missing cell portsgatecat2021-05-212-2/+3
* interchange: Add LUTRAM testgatecat2021-05-216-0/+169
* interchange: Preliminary implementation of macro expansiongatecat2021-05-213-0/+116
* interchange: Add macro param map rules to chipdbgatecat2021-05-211-0/+24
* interchange: Add macro data to chipdbgatecat2021-05-211-1/+51
* Merge pull request #712 from YosysHQ/gatecat/rr-heatmapgatecat2021-05-216-3/+64
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| * router2: Add heatmap by routing resource typegatecat2021-05-206-3/+64
* | Merge pull request #711 from acomodi/interchange-site-to-pseudo-pipsgatecat2021-05-203-4/+29
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| * gh-actions: interchange: use commit sha as cache keyAlessandro Comodi2021-05-201-4/+10
| * bump interchange schemaAlessandro Comodi2021-05-201-0/+0
| * interchange: phys: add site instance idstr for pseudo tile PIPsAlessandro Comodi2021-05-191-0/+19
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* Run clangformatgatecat2021-05-163-6/+8
* Merge pull request #708 from Ravenslofty/mistral-getchipnamegatecat2021-05-151-1/+1
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| * mistral: add getChipNameLofty2021-05-151-1/+1
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* Merge pull request #707 from gatecat/cyclonevgatecat2021-05-1531-9/+4222
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| * Update READMEgatecat2021-05-151-0/+1
| * mistral: Add MISTRAL_CLKBUF cell typegatecat2021-05-155-1/+15
| * ci: Use GH only for Mistral and fpga-interchangegatecat2021-05-153-2/+58
| * mistral: Tidying upgatecat2021-05-1512-12/+13
| * mistral: Make router2 the defaultgatecat2021-05-151-1/+1
| * router2: Hacky workaround for slow Cyclone V convergencegatecat2021-05-151-3/+3
| * mistral: Speed up bel binding and checkinggatecat2021-05-151-4/+18
| * mistral: Workaround for weird SCLR issuegatecat2021-05-151-0/+7
| * mistral: Fix ENA and ACLR bitstream generationgatecat2021-05-154-4/+11
| * mistral: Disable global buffers that are currently brokengatecat2021-05-151-0/+2
| * router2: Reduce verbosity when debugginggatecat2021-05-151-0/+2
| * mistral: Compensate for EF_SEL mirroring in validity checkgatecat2021-05-151-2/+2
| * mistral: Fix EF_SEL and BTO_DISgatecat2021-05-152-4/+5
| * mistral: PKREG bits appear to be mirrored within a half?gatecat2021-05-151-2/+3
| * mistral: Debugging flipflopsgatecat2021-05-151-3/+4
| * mistral: Trim SDATA if SLOAD is lowgatecat2021-05-151-0/+9
| * mistral: FF&CLKBUF fixes, part 1gatecat2021-05-152-1/+10
| * mistral: First pass at FF and CLKBUF bitgengatecat2021-05-152-18/+115
| * mistral: Account for TD input count limitgatecat2021-05-154-9/+128
| * msitral: Fix pip iterator Python bindingsgatecat2021-05-151-2/+2
| * mistral: Implement PIP locations, toogatecat2021-05-151-1/+1
| * mistral: Implement bounding boxes for router2gatecat2021-05-152-1/+15
| * mistral: Debugging carry chain issuesgatecat2021-05-152-13/+34
| * mistral: Adding FF control set reservationgatecat2021-05-153-58/+148
| * mistral: Carry fixesgatecat2021-05-152-3/+16
| * mistral: Carry debugginggatecat2021-05-153-41/+11
| * mistral: Write arith mode to bitstream (not yet functional)gatecat2021-05-152-2/+18
| * mistral: First pass at carry packinggatecat2021-05-154-8/+82
| * mistral: FF validity checking fixesgatecat2021-05-151-7/+13
| * mistral: Fix constant trimminggatecat2021-05-152-1/+2
| * mistral: Write LUT initsgatecat2021-05-152-1/+72
| * mistral: Add some IO configurationgatecat2021-05-151-0/+30
| * mistral: Setting some more boilerplate bitsgatecat2021-05-153-1/+118
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