iCE40/nextpnr - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	interchange: Implement getWireType	gatecat	2021-04-30	3	-1/+20
*	interchange: Add wire types to chipdb	gatecat	2021-04-30	1	-1/+17
*	Merge pull request #689 from adamgreig/ecp5-alu	gatecat	2021-04-29	3	-1/+140
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\| *	Only set CIBOUT_BYP on MULTs that are not feeding an ALU.	Adam Greig	2021-04-29	1	-1/+1
\| *	Add check_alu to Ecp5Packer	Adam Greig	2021-04-29	1	-15/+123
\| *	Add relative constraints to position MULT18X18D near connected ALU54B.	Adam Greig	2021-04-29	2	-0/+29
\| *	Add ALU54B.REG_OPCODEOP1_1_CLK parameter support	Adam Greig	2021-04-29	1	-0/+2
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*	Merge pull request #685 from YosysHQ/gatecat/nexus-routing	gatecat	2021-04-25	1	-4/+1
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\| *	nexus: Enable placeAllAtOnce	gatecat	2021-04-25	1	-4/+1
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*	Merge pull request #683 from antmicro/interchange-allow-loc-keyword	gatecat	2021-04-20	1	-2/+4
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\| *	interchange: allow LOC keyword in XDC files	Jan Kowalewski	2021-04-20	1	-2/+4
* \|	Merge pull request #682 from YosysHQ/gatecat/default-cellpins	gatecat	2021-04-20	6	-8/+81
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\| * \|	interchange: Bump versions	gatecat	2021-04-20	2	-1/+1
\| * \|	interchange: Handle disconnected/missing cell pins	gatecat	2021-04-19	3	-6/+56
\| * \|	interchange: Add default cell connections to chipdb	gatecat	2021-04-19	1	-1/+24
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* \|	Merge pull request #681 from YosysHQ/gatecat/more-pybindings	gatecat	2021-04-15	2	-0/+8
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\| * \|	Add Python bindings for placement tests	gatecat	2021-04-15	2	-0/+8
* \| \|	Merge pull request #680 from YosysHQ/gatecat/fix-util	gatecat	2021-04-15	1	-2/+2
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\| * \|	Fix utilisation report when bel buckets are used	gatecat	2021-04-15	1	-2/+2
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* \|	Merge pull request #678 from acomodi/initial-fasm-generation	gatecat	2021-04-14	21	-71/+136
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\| * \|	gh-actions: increase python-fpga-interchange tag version	Alessandro Comodi	2021-04-14	1	-1/+1
\| * \|	interchange: add FASM generation target and clean-up tests	Alessandro Comodi	2021-04-14	20	-70/+135
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* \|	Merge pull request #679 from YosysHQ/gatecat/disable-absl	gatecat	2021-04-14	11	-63/+54
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\| *	ci: Re-enable abseil for interchange CI	gatecat	2021-04-14	1	-1/+1
\| *	Hash table refactoring	gatecat	2021-04-14	10	-62/+53
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*	Merge pull request #677 from YosysHQ/gatecat/ppip-no-input	gatecat	2021-04-13	1	-14/+35
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\| *	interchange: Allow pseudo-cells with no input pins	gatecat	2021-04-13	1	-14/+35
* \|	Merge pull request #676 from YosysHQ/gatecat/fix-sta-crash	gatecat	2021-04-13	2	-58/+73
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\| *	timing: Fix domain init when loops are present	gatecat	2021-04-13	2	-58/+73
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*	Merge pull request #674 from adamgreig/heap-spreader-fix	gatecat	2021-04-12	1	-0/+4
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\| *	HeAP: Skip high-strength cells in both cell loops.	Adam Greig	2021-04-12	1	-0/+4
* \|	Merge pull request #673 from YosysHQ/gatecat/fix-fast-bels-ref	gatecat	2021-04-12	1	-14/+18
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\| *	fast_bels: Don't return pointer that might become invalid	gatecat	2021-04-12	1	-14/+18
* \|	clangformat	gatecat	2021-04-12	8	-133/+134
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*	Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vcc	gatecat	2021-04-09	1	-6/+10
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\| *	interchange: Disambiguate cell and bel pins when creating Vcc ties	gatecat	2021-04-09	1	-6/+10
* \|	Merge pull request #669 from YosysHQ/gatecat/prjoxide-pin	gatecat	2021-04-09	2	-0/+3
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\| *	interchange: Pin prjoxide commit	gatecat	2021-04-09	2	-0/+3
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*	Merge pull request #667 from YosysHQ/fix_qt	Miodrag Milanović	2021-04-08	1	-0/+4
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\| *	Add same fix as in issue #373	Miodrag Milanovic	2021-04-08	1	-0/+4
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*	Merge pull request #665 from cr1901/optional-lto	gatecat	2021-04-07	1	-2/+13
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\| *	Add CMake option to enable IPO (enabled by default).	William D. Jones	2021-04-07	1	-2/+13
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*	Merge pull request #659 from litghost/pseudo_pip_fixes	gatecat	2021-04-06	11	-66/+882
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\| *	[interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.	Keith Rothman	2021-04-06	1	-1/+16
\| *	Don't fail-fast for GH actions to allow for easier CI debugging.	Keith Rothman	2021-04-06	1	-0/+3
\| *	[interchange] Remove requirement to have wire_lut.	Keith Rothman	2021-04-06	3	-6/+7
\| *	[interchange] Fix invalid use of local variables due to refactoring.	Keith Rothman	2021-04-06	3	-6/+7
\| *	[interchange] Prevent site router from generating incorrect LUTs.	Keith Rothman	2021-04-06	3	-42/+102
\| *	[interchange] Scale edge cost of pseudo pips.	Keith Rothman	2021-04-06	2	-5/+12
\| *	[interchange] Fix missing inline methods in site_arch.impl.h	Keith Rothman	2021-04-06	2	-8/+9