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* router2: Update route delays even when routes are congestedgatecat2021-07-281-1/+43
* timing: Allow overriding of route delaysgatecat2021-07-282-3/+10
* Merge pull request #780 from YosysHQ/gatecat/fix-io-invgatecat2021-07-261-13/+32
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| * interchange: Search backwards for IO macro placements, toogatecat2021-07-261-13/+32
* | Merge pull request #779 from YosysHQ/gatecat/ic-import-fixgatecat2021-07-261-5/+0
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| * interchange: Don't attempt to import instances as modulesgatecat2021-07-261-5/+0
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* Merge pull request #775 from YosysHQ/gatecat/fix-io-checksgatecat2021-07-261-6/+16
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| * interchange: Check IO validity after all are placedgatecat2021-07-231-6/+16
* | Merge pull request #777 from YosysHQ/gatecat/gui-fixesgatecat2021-07-255-5/+20
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| * gui: Fix some typosgatecat2021-07-252-5/+5
| * gui: Implement about dialoggatecat2021-07-254-0/+15
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* Merge pull request #757 from antmicro/lut-mapping-cachegatecat2021-07-228-74/+510
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| * Added an option to disable the LUT mapping cacheMaciej Kurc2021-07-225-8/+16
| * Added more code comments, formatted the codeMaciej Kurc2021-07-226-123/+124
| * Added computing and reporting LUT mapping cache sizeMaciej Kurc2021-07-162-0/+37
| * Fixed assertion typosMaciej Kurc2021-07-161-2/+2
| * Migrated C arrays to std::array containers.Maciej Kurc2021-07-162-9/+31
| * LUT mapping ceche optimizations 2Maciej Kurc2021-07-163-93/+17
| * LUT mapping cache optimizations 1Maciej Kurc2021-07-162-32/+48
| * Working site LUT mapping cacheMaciej Kurc2021-07-167-42/+470
* | Merge pull request #772 from antmicro/xdc_parsegatecat2021-07-211-0/+7
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| * | Add dummy function to parse creat_clock in XDC filesMaciej Dudek2021-07-211-0/+7
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* | Merge pull request #768 from YosysHQ/gatecat/fix-gui-errorgatecat2021-07-212-11/+62
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| * | gui: Improve Fatal Error messagegatecat2021-07-202-11/+62
* | | clangformatgatecat2021-07-211-1/+1
* | | Merge pull request #770 from YosysHQ/gatecat/empty-idstringlistgatecat2021-07-201-1/+1
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| * | | Fix definition of an empty IdStringListgatecat2021-07-201-1/+1
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* | | Merge pull request #771 from YosysHQ/gatecat/ice40-ip-no-busaddr74gatecat2021-07-201-3/+4
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| * | ice40: Use default value when IP is missing BUS_ADDR74 parametergatecat2021-07-201-3/+4
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* | Merge pull request #767 from YosysHQ/gatecat/ic-pref-constgatecat2021-07-201-1/+10
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| * | interchange: Fix preferred constant handling when canInvertgatecat2021-07-201-1/+10
* | | Merge pull request #766 from pepijndevos/pythongatecat2021-07-172-4/+2
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| * | | remove generic leftover in gowinPepijn de Vos2021-07-171-2/+2
| * | | remove generic leftover in gowinPepijn de Vos2021-07-171-2/+0
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* | | Merge pull request #764 from acomodi/fix-pseudo-pipsgatecat2021-07-151-8/+18
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| * | interchange: disallow pseudo-pip on same nets if tile has lutsAlessandro Comodi2021-07-151-8/+18
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* | Merge pull request #762 from antmicro/testarch_timinggatecat2021-07-142-2/+2
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| * | [interchange] Update chipdb and python-fpga-interchange versionsMaciej Dudek2021-07-142-2/+2
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* | Merge pull request #761 from acomodi/interchange-constrsgatecat2021-07-125-13/+174
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| * | interchange: xdc and place constr: address review commentsAlessandro Comodi2021-07-123-23/+13
| * | interchange: xdc: add get_cells commandAlessandro Comodi2021-07-121-13/+70
| * | interchange: add constraints constraints application routineAlessandro Comodi2021-07-124-0/+114
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* | Merge pull request #760 from YosysHQ/gatecat/xcup-ibufdsgatecat2021-07-122-5/+16
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| * | interchange: Skip IO ports in dedicated routing checkgatecat2021-07-121-0/+8
| * | interchange: Debug IO port validity check failuresgatecat2021-07-122-3/+5
| * | interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDSgatecat2021-07-121-3/+4
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* | Merge pull request #759 from pepijndevos/gw1ndbgatecat2021-07-111-1/+8
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| * | GW1NR is not a seperate family, but GW1NS isPepijn de Vos2021-07-111-1/+8
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* | Merge pull request #758 from YosysHQ/gatecat/hist-oobgatecat2021-07-111-1/+6
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| * | timing: Fix out-of-bounds histogram bins in all casesgatecat2021-07-101-1/+6
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