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* github-actions: add basic CI to test FPGA interchangeAlessandro Comodi2021-03-162-0/+74
* fpga_interchange: re-add README with updated instructionsAlessandro Comodi2021-03-161-0/+69
* fpga_interchange: tests: add techmap optional source fileAlessandro Comodi2021-03-164-3/+19
* fpga_interchange: add bbasm step and archcheckAlessandro Comodi2021-03-167-41/+78
* fpga_interchange: address review commentsAlessandro Comodi2021-03-164-32/+91
* fpga_interchange: tests: added comment and fixed XDCAlessandro Comodi2021-03-1616-29/+74
* fpga_interchange: chipdb: use generic patching functionAlessandro Comodi2021-03-163-41/+96
* fpga_interchange: cmake: generate only one device familyAlessandro Comodi2021-03-169-49/+72
* fpga_interchange: tests: add cmake functionsAlessandro Comodi2021-03-1627-50/+215
* bump fpga_interchange_schemaAlessandro Comodi2021-03-161-0/+0
* fpga_intrchange: add cmake infrastructure to generate chipdbsAlessandro Comodi2021-03-166-133/+122
* Merge pull request #626 from YosysHQ/missing-includesgatecat2021-03-162-0/+5
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| * Add missing includes to fix WASI build.whitequark2021-03-162-0/+5
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* Merge pull request #625 from litghost/use_namespace_macrogatecat2021-03-1514-28/+34
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| * Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-1514-28/+34
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* Merge pull request #621 from litghost/fix_header_nightmaregatecat2021-03-1549-2467/+3267
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| * Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-1549-2467/+3267
* | Merge pull request #624 from YosysHQ/gatecat/fix-623gatecat2021-03-151-0/+2
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| * opt-timing: Skip undriven netsgatecat2021-03-151-0/+2
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* Merge pull request #620 from litghost/handle_partial_routedgatecat2021-03-122-28/+54
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| * Add support for partially routed nets from the placer in router2.Keith Rothman2021-03-122-28/+54
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* Merge pull request #618 from YosysHQ/no-absl-on-wasigatecat2021-03-121-1/+3
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| * CMake: Don't include Abseil if it is not used.whitequark2021-03-121-1/+3
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* Merge pull request #615 from litghost/add_lookahead_diag_to_router2gatecat2021-03-101-13/+41
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| * Add diagnostic prints to debug lookahead performance.Keith Rothman2021-03-101-13/+41
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* Merge pull request #617 from YosysHQ/no-absl-on-wasigatecat2021-03-102-2/+10
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| * Only depend on Abseil in threaded builds.whitequark2021-03-102-2/+10
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* Merge pull request #607 from litghost/add_absl_flat_hash_mapgatecat2021-03-094-1/+10
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| * Add absl::flat_hash_map.Keith Rothman2021-03-014-1/+10
* | Merge pull request #609 from YosysHQ/gatecat/sta-v2gatecat2021-03-0910-254/+943
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| * | timing: Integration tweaksgatecat2021-03-054-4/+9
| * | timing: Skip route delays for unplaced/nullptr cellsgatecat2021-03-041-1/+6
| * | timing: Replace all users of criticality with new enginegatecat2021-03-046-241/+58
| * | timing: Use new engine in SA except for budget-based modegatecat2021-03-041-10/+7
| * | timing: Use new engine for HeAPgatecat2021-03-043-14/+19
| * | timing: Add support for critical path printinggatecat2021-03-042-0/+69
| * | timing: Slack and criticality computationgatecat2021-03-042-0/+47
| * | timing: Produce plausible Fmax figuregatecat2021-03-042-1/+12
| * | timing: Add Fmax printing for debugginggatecat2021-03-042-0/+23
| * | timing: Add backwards path walkinggatecat2021-03-043-1/+71
| * | timing: Add forward path walkinggatecat2021-03-042-0/+105
| * | timing: Compute domain pairsgatecat2021-03-042-13/+59
| * | timing: Add port-domain trackinggatecat2021-03-043-1/+115
| * | timing: Add topological sort from Yosysgatecat2021-03-043-0/+130
| * | timing: Import cell delays to our own structuresgatecat2021-03-042-0/+123
| * | timing: Data structures for STA rewritegatecat2021-03-041-0/+122
* | | Merge pull request #613 from YosysHQ/gatecat/nexus-dphygatecat2021-03-086-2/+121
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| * | | nexus: Support for hard DPHYgatecat2021-03-084-2/+73
| * | | nexus: Add pin definitions for DPHYgatecat2021-03-083-0/+48
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* | | Merge pull request #612 from YosysHQ/gatecat/router2-bb-fixgatecat2021-03-081-1/+1
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