aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* interchange: Add more global cell infogatecat2021-05-071-1/+14
* Merge pull request #697 from YosysHQ/gatecat/router2-dynamic-bb-expandgatecat2021-05-061-23/+61
|\
| * router2: Reserve wires in more complex casesgatecat2021-05-061-13/+39
| * router2: Dynamicly expand bounding box based on congestiongatecat2021-05-061-10/+22
|/
* Revert "nexus: Enable placeAllAtOnce"gatecat2021-05-061-1/+4
* Merge pull request #688 from YosysHQ/gatecat/new-cluster-apigatecat2021-05-0626-391/+411
|\
| * Add stub cluster API impl for remaining archesgatecat2021-05-067-2/+34
| * nexus: Use new cluster APIgatecat2021-05-063-13/+17
| * base_arch: Fix typo in getClusterPlacementgatecat2021-05-061-1/+1
| * ecp5: Use new cluster APIgatecat2021-05-063-20/+29
| * Update placers to use new cluster APIsgatecat2021-05-0610-346/+151
| * Add default base implementation of cluster APIgatecat2021-05-066-7/+104
| * Add BaseClusterInfo for base implementationgatecat2021-05-061-0/+44
| * arch_api: Outline of new cluster APIgatecat2021-05-064-14/+43
|/
* Merge pull request #692 from davidcorrigan714/patch-1gatecat2021-05-011-2/+2
|\
| * Update bits.hDavid Corrigan2021-04-301-2/+2
|/
* clangformatgatecat2021-04-301-40/+30
* Merge pull request #664 from YosysHQ/gatecat/nexus-countergatecat2021-04-308-3/+61
|\
| * interchange/nexus: Add counter examplegatecat2021-04-308-3/+61
|/
* Merge pull request #690 from YosysHQ/gatecat/interchange-wire-typesgatecat2021-04-305-4/+39
|\
| * interchange: Bump versionsgatecat2021-04-301-2/+2
| * interchange: Implement getWireTypegatecat2021-04-303-1/+20
| * interchange: Add wire types to chipdbgatecat2021-04-301-1/+17
|/
* Merge pull request #689 from adamgreig/ecp5-alugatecat2021-04-293-1/+140
|\
| * Only set CIBOUT_BYP on MULTs that are not feeding an ALU.Adam Greig2021-04-291-1/+1
| * Add check_alu to Ecp5PackerAdam Greig2021-04-291-15/+123
| * Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-292-0/+29
| * Add ALU54B.REG_OPCODEOP1_1_CLK parameter supportAdam Greig2021-04-291-0/+2
|/
* Merge pull request #685 from YosysHQ/gatecat/nexus-routinggatecat2021-04-251-4/+1
|\
| * nexus: Enable placeAllAtOncegatecat2021-04-251-4/+1
|/
* Merge pull request #683 from antmicro/interchange-allow-loc-keywordgatecat2021-04-201-2/+4
|\
| * interchange: allow LOC keyword in XDC filesJan Kowalewski2021-04-201-2/+4
* | Merge pull request #682 from YosysHQ/gatecat/default-cellpinsgatecat2021-04-206-8/+81
|\ \
| * | interchange: Bump versionsgatecat2021-04-202-1/+1
| * | interchange: Handle disconnected/missing cell pinsgatecat2021-04-193-6/+56
| * | interchange: Add default cell connections to chipdbgatecat2021-04-191-1/+24
|/ /
* | Merge pull request #681 from YosysHQ/gatecat/more-pybindingsgatecat2021-04-152-0/+8
|\ \
| * | Add Python bindings for placement testsgatecat2021-04-152-0/+8
* | | Merge pull request #680 from YosysHQ/gatecat/fix-utilgatecat2021-04-151-2/+2
|\ \ \ | |/ / |/| |
| * | Fix utilisation report when bel buckets are usedgatecat2021-04-151-2/+2
|/ /
* | Merge pull request #678 from acomodi/initial-fasm-generationgatecat2021-04-1421-71/+136
|\ \
| * | gh-actions: increase python-fpga-interchange tag versionAlessandro Comodi2021-04-141-1/+1
| * | interchange: add FASM generation target and clean-up testsAlessandro Comodi2021-04-1420-70/+135
| |/
* | Merge pull request #679 from YosysHQ/gatecat/disable-abslgatecat2021-04-1411-63/+54
|\ \ | |/ |/|
| * ci: Re-enable abseil for interchange CIgatecat2021-04-141-1/+1
| * Hash table refactoringgatecat2021-04-1410-62/+53
|/
* Merge pull request #677 from YosysHQ/gatecat/ppip-no-inputgatecat2021-04-131-14/+35
|\
| * interchange: Allow pseudo-cells with no input pinsgatecat2021-04-131-14/+35
* | Merge pull request #676 from YosysHQ/gatecat/fix-sta-crashgatecat2021-04-132-58/+73
|\ \ | |/ |/|
| * timing: Fix domain init when loops are presentgatecat2021-04-132-58/+73
|/
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 19:50:34 +0000