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* ecp5: Working on LVDS inputs for Versa supportDavid Shah2018-07-241-0/+8
* Merge branch 'placeconstr2'Clifford Wolf2018-07-241-0/+10
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| * Typo fixClifford Wolf2018-07-241-1/+1
| * Add CellInfo data for placement constraintsClifford Wolf2018-07-241-0/+10
* | Merge branch 'q3k/pll' into 'master'Serge Bazanski2018-07-249-14/+375
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| * | ice40: after reviewSergiusz Bazanski2018-07-241-1/+0
| * | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pllSergiusz Bazanski2018-07-2426-173/+196
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* | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrDavid Shah2018-07-242-5/+30
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| * | | Add missing implementations of generic Arch methodsClifford Wolf2018-07-242-5/+30
* | | | ecp5: Architecture testing and fixingDavid Shah2018-07-242-1/+11
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* | | Remove implementations of deprecated APIsDavid Shah2018-07-248-77/+9
* | | ice40: Remove use of deprecated APIsDavid Shah2018-07-243-10/+10
* | | common: Remove use of deprecated APIsDavid Shah2018-07-243-29/+24
* | | Remove uphill/downhill bel pins from ice40 dbClifford Wolf2018-07-242-34/+0
* | | Add bbasm target, use as passthru in iCE40 builderDavid Shah2018-07-244-5/+32
* | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrDavid Shah2018-07-244-4/+20
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| * | Add dummy bba mainClifford Wolf2018-07-241-0/+15
| * | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-07-241-2/+25
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| * | | Change G_FRAME color to be significantly darker than G_ACTIVEClifford Wolf2018-07-241-1/+1
| * | | Add G_ARROW (for now same look as G_LINE)Clifford Wolf2018-07-243-3/+4
* | | | ecp5: Support for differential IODavid Shah2018-07-241-1/+15
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* | | ecp5: Set BANKREF to correct VccIODavid Shah2018-07-241-2/+25
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* | timing: Model clock to Q timesDavid Shah2018-07-242-0/+18
* | ice40: Trim BRAM constant inputs, reduces routing congestion around BRAMDavid Shah2018-07-241-0/+3
* | ice40: Fix SPRAM and other primitives in corners other than (0, 0)David Shah2018-07-241-1/+1
| * ice40: fixes before reviewSergiusz Bazanski2018-07-246-47/+14
| * ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-243-69/+40
| * ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-244-16/+22
| * clang-formatSergiusz Bazanski2018-07-244-67/+74
| * ice40: A slightly nicer way to do this.Sergiusz Bazanski2018-07-241-46/+31
| * ice40: Move spliceLUT back to pack.ccSergiusz Bazanski2018-07-243-56/+53
| * ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputsSergiusz Bazanski2018-07-241-0/+24
| * ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-244-74/+59
| * ice40: Emit feed-through LUTs for PLL/LOCKSergiusz Bazanski2018-07-243-5/+159
| * ice40: Fail early on SB_PLL40_*_PAD cellsSergiusz Bazanski2018-07-242-0/+14
| * ice40: Implement emitting PLLsSergiusz Bazanski2018-07-2412-17/+275
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* make update of tree for nets and cells partialMiodrag Milanovic2018-07-232-26/+56
* ecp5: Add some more PIO helper functionsDavid Shah2018-07-232-0/+42
* ecp5: Helper functions for I/O placement and checkingDavid Shah2018-07-233-0/+324
* Proper highlight/selected cleanup on context re-initMiodrag Milanovic2018-07-232-0/+4
* write frequency infoMiodrag Milanovic2018-07-231-0/+1
* always assign budget before placingMiodrag Milanovic2018-07-231-2/+2
* Add Context::archcheck() and "nextpnr-ice40 --test"Clifford Wolf2018-07-235-45/+208
* Remove getBelsByType() APIClifford Wolf2018-07-234-40/+0
* clangformatDavid Shah2018-07-232-4/+5
* ecp5: Add Add getGridDimX(), getGridDimY(), getTileDimZ()David Shah2018-07-231-0/+5
* clangformatClifford Wolf2018-07-232-20/+26
* Add fallback to estimateDelay() in getNetinfoRouteDelay()Clifford Wolf2018-07-231-1/+6
* Add getGridDimX(), getGridDimY(), getTileDimZ() APIClifford Wolf2018-07-233-1/+31
* ecp5: Implement new Grid APIsDavid Shah2018-07-232-0/+50
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