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* ice40: Adding cell utilities for packingDavid Shah2018-06-124-15/+191
* Adding some utilities for packingDavid Shah2018-06-122-0/+100
* ice40: Optimising chipdb buildsDavid Shah2018-06-121-0/+1
* Made gtest work on MINGW with solution from https://github.com/google/googlet...Miodrag Milanovic2018-06-121-4/+4
* Clang format to ignore 3rdparty and fix one fileMiodrag Milanovic2018-06-112-36/+84
* Fix gitignoreMiodrag Milanovic2018-06-111-2/+2
* Added dummy tests per archMiodrag Milanovic2018-06-114-3/+48
* added google tests to 3rdpartyMiodrag Milanovic2018-06-11321-0/+153552
* Added property editor for exampleMiodrag Milanovic2018-06-114-9/+145
* compile QtPropertyBrowserMiodrag Milanovic2018-06-119-11/+42
* Added QtPropertyBrowser sourceMiodrag Milanovic2018-06-11148-0/+35531
* Add "nextpnr.h"Clifford Wolf2018-06-1123-78/+99
* Remove pool, dict, vector namespace aliasesClifford Wolf2018-06-119-89/+95
* Add conflicting=false argument to bind gettersClifford Wolf2018-06-113-9/+11
* Proper looking output in python consoleMiodrag Milanovic2018-06-111-7/+12
* OpenGL library portable way of usingMiodrag Milanovic2018-06-111-1/+2
* Fixed portability issue, now it works on msys2 windows build as wellMiodrag Milanovic2018-06-111-2/+3
* nice way to get main windowMiodrag Milanovic2018-06-102-3/+15
* Draw fpga modelMiodrag Milanovic2018-06-103-13/+67
* Propagate design to widgetMiodrag Milanovic2018-06-103-0/+5
* Pass design to gui, display chip nameMiodrag Milanovic2018-06-108-5/+45
* Improving 5k supportDavid Shah2018-06-104-22/+59
* Fix iCE40 routing graphClifford Wolf2018-06-102-28/+1
* Add support for iCE40 global buffers (currently only for 1k devices)Clifford Wolf2018-06-108-124/+198
* Debugging on icebreakerDavid Shah2018-06-104-11/+217
* Add blinky post-synthesis testbenchClifford Wolf2018-06-103-5/+26
* Fix ice40 pip/switch locked performance issueClifford Wolf2018-06-103-16/+9
* ice40: Set config bits for unused IODavid Shah2018-06-101-1/+19
* ice40: Fix techmapDavid Shah2018-06-101-1/+1
* ice40: Add IO config to bitstreamDavid Shah2018-06-103-17/+93
* ice40: Write logic cell config to bitstreamDavid Shah2018-06-103-7/+60
* ice40: Lock out mutually exclusive pipsDavid Shah2018-06-102-2/+13
* ice40: Start adding routing to asc outputDavid Shah2018-06-101-0/+34
* ice40: Writing an empty ASC fileDavid Shah2018-06-106-1/+141
* ice40: Adding non-routing config bits to databaseDavid Shah2018-06-102-10/+63
* ice40: Add switch data to databaseDavid Shah2018-06-102-6/+95
* Renamed LOC attribute to BEL, fix ice40 IO bel namesClifford Wolf2018-06-093-12/+12
* Adding basic placement constraintsDavid Shah2018-06-094-6/+118
* json: Parse cell attributesDavid Shah2018-06-091-7/+24
* Getting rid of .nil() methods, compare with zero- and default-constructed obj...Clifford Wolf2018-06-094-48/+36
* Add dummy implementations of dummy Chip APIClifford Wolf2018-06-092-1/+94
* Add very basic routerClifford Wolf2018-06-099-46/+370
* Remove writing on sell types to cout (left over debug output?)Clifford Wolf2018-06-091-1/+0
* Improving the Python bindings, particularly the map/pair wrappersDavid Shah2018-06-083-21/+176
* Updating README.mdDavid Shah2018-06-081-3/+12
* python: Fixing builds as importable moduleDavid Shah2018-06-085-0/+21
* Reformat remaining filesDavid Shah2018-06-085-92/+101
* Merged log_ lines in the JSON parserZipCPU2018-06-071-13/+6
* Tried to add fixes *and* update clang-format jsonparse.ccZipCPU2018-06-078-157/+138
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| * clang format for gui related filesMiodrag Milanovic2018-06-066-154/+116
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