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| * common: Improved the random seed initialisation for the contextdx-mon2021-11-191-6/+4
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* Merge pull request #859 from yrabbit/gowin-packagesgatecat2021-11-074-17/+53
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| * gowin: Check the chipdb versionYRabbit2021-11-072-1/+7
| * gowin: use latest Apycula releaseYRabbit2021-11-071-1/+1
| * Merge branch 'master' into gowin-packagesYRabbit2021-11-062-3/+11
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* | Merge pull request #857 from YosysHQ/gatecat/ecp5-ff-iodelgatecat2021-11-052-3/+11
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| * | ecp5: Fix packing of IOFF with IODELAYsgatecat2021-11-052-3/+11
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| * gowin: Use speed from chip base.YRabbit2021-11-053-20/+27
| * gowin: Add partnumbers and packages to the chipdbYRabbit2021-11-043-6/+29
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* Merge pull request #855 from galibert/mastergatecat2021-10-282-4/+3
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| * mistral: Sync with yet another reorganizationOlivier Galibert2021-10-282-4/+3
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* Merge pull request #852 from yrabbit/pr-gowin-alugatecat2021-10-223-6/+226
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| * gowin: Explicitly initialize the y in the clusterYRabbit2021-10-221-0/+5
| * gowin: Add ALU support.YRabbit2021-10-223-6/+221
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* interchange: Bump prjoxide versiongatecat2021-10-201-1/+1
* Merge pull request #851 from galibert/mastergatecat2021-10-193-13/+14
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| * Normalize formattingOlivier Galibert2021-10-192-13/+17
| * mistral: Use the iteratorsOlivier Galibert2021-10-192-12/+9
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* Merge pull request #848 from galibert/mastergatecat2021-10-172-1/+2
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| * Sync mistral version in CIOlivier Galibert2021-10-171-1/+1
| * mistral: Support the new routes-to-bin intermediate tool generationOlivier Galibert2021-10-171-0/+1
* | Merge pull request #849 from galibert/cyclonev-oscillatorgatecat2021-10-174-3/+15
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| * mistral: Add internal oscillator supportOlivier Galibert2021-10-174-3/+15
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* Merge pull request #847 from galibert/mastergatecat2021-10-154-0/+17
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| * cyclonev_hps_interface_mpu_general_purpose: Use a id_ identifierOlivier Galibert2021-10-152-1/+3
| * mistral: Add support for cyclonev_hps_interface_mpu_general_purposeOlivier Galibert2021-10-143-0/+15
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* Merge pull request #845 from YosysHQ/gatecat/mlab-cluster-fixgatecat2021-10-112-2/+9
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| * mistral: Fix MLAB clusteringgatecat2021-10-112-2/+9
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* clangformatgatecat2021-10-112-29/+42
* Merge pull request #843 from Ravenslofty/lofty/mistral-basic-timinggatecat2021-10-113-21/+256
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| * mistral: very basic timing infoLofty2021-10-104-22/+257
* | Merge pull request #844 from pepijndevos/patch-2gatecat2021-10-101-2/+2
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| * | Gowin: more clearly mark dummy pipsPepijn de Vos2021-10-101-2/+2
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* | Merge pull request #842 from yrabbit/delaysgatecat2021-10-093-12/+40
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| * \ Merge branch 'master' into delaysYRabbit2021-10-091-18/+6
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| * | | gowin: Replace the zero delays with reasonable values.YRabbit2021-10-093-12/+40
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* | | router2: Disable criticality sorting towards end of routinggatecat2021-10-091-1/+1
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* | Merge pull request #841 from Ravenslofty/lofty/mistral-cleanupgatecat2021-10-081-18/+6
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| * mistral: clean up bel init slightlyLofty2021-10-081-18/+6
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* hashlib: Support for std::array keysgatecat2021-10-071-0/+13
* Merge pull request #839 from yrabbit/wide-lutsgatecat2021-10-077-9/+434
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| * gowin: add support for wide LUTs.YRabbit2021-10-077-9/+434
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* Merge pull request #837 from YosysHQ/gatecat/mistral-mlab-2gatecat2021-10-058-21/+235
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| * mistral: Adding support for MLABs as memorygatecat2021-10-058-21/+235
* | Merge pull request #836 from YosysHQ/gatecat/mistral-mlabgatecat2021-10-032-19/+38
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| * mistral: Add bel pins for MLAB write portgatecat2021-10-032-19/+38
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* Merge pull request #834 from YosysHQ/gatecat/cygwingatecat2021-10-011-1/+1
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| * Fix Cygwin buildgatecat2021-10-011-1/+1
* | Merge pull request #833 from antmicro/interchange-fix-uninitialized-memory-buggatecat2021-10-011-1/+1
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| * interchange: fix uninitialized memory bug in cluster placementAlessandro Comodi2021-10-011-1/+1
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