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| * refactor: ArcBounds -> BoundingBoxgatecat2022-12-0726-57/+57
* | Merge pull request #1055 from yrabbit/pll-pinsmyrtle2022-12-065-16/+140
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| * gowin: change the way networks are handledYRabbit2022-12-061-7/+8
| * Merge branch 'master' into pll-pinsYRabbit2022-12-0413-17/+17
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| * | gowin: add PLL pins processingYRabbit2022-12-045-10/+133
* | | Merge pull request #1056 from YosysHQ/gatecat/generic-fix-constsmyrtle2022-12-061-0/+3
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| * | viaduct: Fix constant connectivitygatecat2022-12-061-0/+3
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* | Merge pull request #1054 from YosysHQ/gatecat/api-add-constmyrtle2022-12-0413-17/+17
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| * Unbreak CIgatecat2022-12-021-5/+5
| * api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-0212-12/+12
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* Merge pull request #1048 from yrabbit/chipdb-cfgmyrtle2022-12-023-5/+23
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| * gowin: update the apicula versionYRabbit2022-12-021-1/+1
| * Merge branch 'master' into chipdb-cfgYRabbit2022-12-021-2/+2
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* | Merge pull request #1053 from YosysHQ/gatecat/pbfixmyrtle2022-11-281-2/+2
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| * | ecp5: Fix Python bindings for pip iteratorsgatecat2022-11-281-2/+2
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| * gowin: add information about pin configurationsYRabbit2022-11-252-4/+22
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* Merge pull request #1045 from yrabbit/unused-portsmyrtle2022-11-202-0/+16
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| * gowin: mark the PLL ports that are not in useYRabbit2022-11-202-0/+16
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* Merge pull request #1042 from yrabbit/add-z1myrtle2022-11-121-1/+1
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| * gowin: add support for a more common chipYRabbit2022-11-121-1/+1
* | Merge pull request #1040 from yrabbit/pll-stage0myrtle2022-11-116-8/+210
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| * gowin: use ctx->idf() a bitYRabbit2022-11-112-41/+17
| * gowin: add initial PLL supportYRabbit2022-11-106-1/+227
* | Merge pull request #1041 from YosysHQ/gatecat/fix-copy-warningmyrtle2022-11-101-0/+1
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| * | Fix "implicit copy constructor for 'Property' is deprecated"gatecat2022-11-101-0/+1
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* / fabulous: Tweak delay estimategatecat2022-11-101-0/+1
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* Merge pull request #1037 from YosysHQ/fix_python_verMiodrag Milanović2022-10-241-1/+2
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| * Fix python version in CIMiodrag Milanovic2022-10-241-1/+2
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* Update CI scriptMiodrag Milanovic2022-10-241-6/+6
* run clangformatgatecat2022-10-172-7/+12
* Merge pull request #1034 from lushaylabs/support-windows-crlfmyrtle2022-10-171-4/+4
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| * support windows line endingsLushay Labs2022-10-091-4/+4
* | Merge pull request #1035 from tyler274/patch-1myrtle2022-10-171-1/+1
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| * Correct Not Equal operator implementation in ice40Tyler2022-10-171-1/+1
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* Merge pull request #1032 from davidlattimore/registered-output-xformmyrtle2022-10-052-0/+9
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| * nexus: Transform registered output parametersDavid Lattimore2022-10-052-0/+9
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* Merge pull request #1031 from YosysHQ/gatecat/fab-nextmyrtle2022-09-305-2/+130
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| * fabulous: Pack, validity check and FASM support for muxesgatecat2022-09-304-5/+84
| * fabulous: Add split MUX belsgatecat2022-09-302-1/+50
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* Merge pull request #1030 from YosysHQ/gatecat/ice40-dsp25_10-fixmyrtle2022-09-261-15/+21
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| * ice40: Fix handling of carry out route-thru via 25,14gatecat2022-09-261-15/+21
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* Merge pull request #1029 from airskywater/airskywater-patch-1myrtle2022-09-241-0/+6
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| * Modify code to meet the code style preferencesairskywater2022-09-241-4/+4
| * Add more sanity check for pointersairskywater2022-09-241-0/+1
| * fix runtime segmentation faultairskywater2022-09-241-0/+5
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* Merge pull request #1019 from antmicro/support-clock-relationsmyrtle2022-09-204-11/+300
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| * Added the --ignore-rel-clk option to control timing checks for cross-domain p...Maciej Kurc2022-09-203-115/+108
| * Code cleanupMaciej Kurc2022-08-312-68/+39
| * Added timing check for cross-domain paths for related clocksMaciej Kurc2022-08-311-4/+104
| * Augmented TimingAnalyser class with detection of clock to clock relationsMaciej Kurc2022-08-302-7/+225
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