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* Merge pull request #702 from YosysHQ/gatecat/interchange-fix-bbgatecat2021-05-112-3/+3
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| * router2: Fix a typogatecat2021-05-111-1/+1
| * interchange: Fix bounding box computationgatecat2021-05-111-2/+2
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* Merge pull request #701 from YosysHQ/gatecat/finer-debuggatecat2021-05-111-0/+11
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| * command: Allow debug output for just placer or routergatecat2021-05-111-0/+11
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* Merge pull request #695 from acomodi/fix-illegal-site-thrugatecat2021-05-102-2/+25
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| * interchange: site router: fix log messagesAlessandro Comodi2021-05-101-3/+3
| * interchange: site router: fix illegal site thru pathsAlessandro Comodi2021-05-102-0/+23
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* Merge pull request #694 from YosysHQ/gatecat/interchange-glbroutegatecat2021-05-075-2/+337
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| * interchange: Bump versiongatecat2021-05-071-1/+1
| * interchange: Adding a basic global buffer placergatecat2021-05-073-32/+132
| * interchange: Initial global routing implementationgatecat2021-05-073-0/+222
| * interchange: Add more global cell infogatecat2021-05-071-1/+14
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* Merge pull request #697 from YosysHQ/gatecat/router2-dynamic-bb-expandgatecat2021-05-061-23/+61
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| * router2: Reserve wires in more complex casesgatecat2021-05-061-13/+39
| * router2: Dynamicly expand bounding box based on congestiongatecat2021-05-061-10/+22
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* Revert "nexus: Enable placeAllAtOnce"gatecat2021-05-061-1/+4
* Merge pull request #688 from YosysHQ/gatecat/new-cluster-apigatecat2021-05-0626-391/+411
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| * Add stub cluster API impl for remaining archesgatecat2021-05-067-2/+34
| * nexus: Use new cluster APIgatecat2021-05-063-13/+17
| * base_arch: Fix typo in getClusterPlacementgatecat2021-05-061-1/+1
| * ecp5: Use new cluster APIgatecat2021-05-063-20/+29
| * Update placers to use new cluster APIsgatecat2021-05-0610-346/+151
| * Add default base implementation of cluster APIgatecat2021-05-066-7/+104
| * Add BaseClusterInfo for base implementationgatecat2021-05-061-0/+44
| * arch_api: Outline of new cluster APIgatecat2021-05-064-14/+43
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* Merge pull request #692 from davidcorrigan714/patch-1gatecat2021-05-011-2/+2
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| * Update bits.hDavid Corrigan2021-04-301-2/+2
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* clangformatgatecat2021-04-301-40/+30
* Merge pull request #664 from YosysHQ/gatecat/nexus-countergatecat2021-04-308-3/+61
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| * interchange/nexus: Add counter examplegatecat2021-04-308-3/+61
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* Merge pull request #690 from YosysHQ/gatecat/interchange-wire-typesgatecat2021-04-305-4/+39
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| * interchange: Bump versionsgatecat2021-04-301-2/+2
| * interchange: Implement getWireTypegatecat2021-04-303-1/+20
| * interchange: Add wire types to chipdbgatecat2021-04-301-1/+17
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* Merge pull request #689 from adamgreig/ecp5-alugatecat2021-04-293-1/+140
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| * Only set CIBOUT_BYP on MULTs that are not feeding an ALU.Adam Greig2021-04-291-1/+1
| * Add check_alu to Ecp5PackerAdam Greig2021-04-291-15/+123
| * Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-292-0/+29
| * Add ALU54B.REG_OPCODEOP1_1_CLK parameter supportAdam Greig2021-04-291-0/+2
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* Merge pull request #685 from YosysHQ/gatecat/nexus-routinggatecat2021-04-251-4/+1
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| * nexus: Enable placeAllAtOncegatecat2021-04-251-4/+1
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* Merge pull request #683 from antmicro/interchange-allow-loc-keywordgatecat2021-04-201-2/+4
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| * interchange: allow LOC keyword in XDC filesJan Kowalewski2021-04-201-2/+4
* | Merge pull request #682 from YosysHQ/gatecat/default-cellpinsgatecat2021-04-206-8/+81
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| * | interchange: Bump versionsgatecat2021-04-202-1/+1
| * | interchange: Handle disconnected/missing cell pinsgatecat2021-04-193-6/+56
| * | interchange: Add default cell connections to chipdbgatecat2021-04-191-1/+24
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* | Merge pull request #681 from YosysHQ/gatecat/more-pybindingsgatecat2021-04-152-0/+8
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| * | Add Python bindings for placement testsgatecat2021-04-152-0/+8
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