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| * Add check_alu to Ecp5PackerAdam Greig2021-04-291-15/+123
| * Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-292-0/+29
| * Add ALU54B.REG_OPCODEOP1_1_CLK parameter supportAdam Greig2021-04-291-0/+2
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* Merge pull request #685 from YosysHQ/gatecat/nexus-routinggatecat2021-04-251-4/+1
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| * nexus: Enable placeAllAtOncegatecat2021-04-251-4/+1
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* Merge pull request #683 from antmicro/interchange-allow-loc-keywordgatecat2021-04-201-2/+4
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| * interchange: allow LOC keyword in XDC filesJan Kowalewski2021-04-201-2/+4
* | Merge pull request #682 from YosysHQ/gatecat/default-cellpinsgatecat2021-04-206-8/+81
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| * | interchange: Bump versionsgatecat2021-04-202-1/+1
| * | interchange: Handle disconnected/missing cell pinsgatecat2021-04-193-6/+56
| * | interchange: Add default cell connections to chipdbgatecat2021-04-191-1/+24
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* | Merge pull request #681 from YosysHQ/gatecat/more-pybindingsgatecat2021-04-152-0/+8
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| * | Add Python bindings for placement testsgatecat2021-04-152-0/+8
* | | Merge pull request #680 from YosysHQ/gatecat/fix-utilgatecat2021-04-151-2/+2
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| * | Fix utilisation report when bel buckets are usedgatecat2021-04-151-2/+2
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* | Merge pull request #678 from acomodi/initial-fasm-generationgatecat2021-04-1421-71/+136
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| * | gh-actions: increase python-fpga-interchange tag versionAlessandro Comodi2021-04-141-1/+1
| * | interchange: add FASM generation target and clean-up testsAlessandro Comodi2021-04-1420-70/+135
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* | Merge pull request #679 from YosysHQ/gatecat/disable-abslgatecat2021-04-1411-63/+54
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| * ci: Re-enable abseil for interchange CIgatecat2021-04-141-1/+1
| * Hash table refactoringgatecat2021-04-1410-62/+53
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* Merge pull request #677 from YosysHQ/gatecat/ppip-no-inputgatecat2021-04-131-14/+35
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| * interchange: Allow pseudo-cells with no input pinsgatecat2021-04-131-14/+35
* | Merge pull request #676 from YosysHQ/gatecat/fix-sta-crashgatecat2021-04-132-58/+73
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| * timing: Fix domain init when loops are presentgatecat2021-04-132-58/+73
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* Merge pull request #674 from adamgreig/heap-spreader-fixgatecat2021-04-121-0/+4
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| * HeAP: Skip high-strength cells in both cell loops.Adam Greig2021-04-121-0/+4
* | Merge pull request #673 from YosysHQ/gatecat/fix-fast-bels-refgatecat2021-04-121-14/+18
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| * fast_bels: Don't return pointer that might become invalidgatecat2021-04-121-14/+18
* | clangformatgatecat2021-04-128-133/+134
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* Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vccgatecat2021-04-091-6/+10
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| * interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
* | Merge pull request #669 from YosysHQ/gatecat/prjoxide-pingatecat2021-04-092-0/+3
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| * interchange: Pin prjoxide commitgatecat2021-04-092-0/+3
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* Merge pull request #667 from YosysHQ/fix_qtMiodrag Milanović2021-04-081-0/+4
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| * Add same fix as in issue #373Miodrag Milanovic2021-04-081-0/+4
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* Merge pull request #665 from cr1901/optional-ltogatecat2021-04-071-2/+13
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| * Add CMake option to enable IPO (enabled by default).William D. Jones2021-04-071-2/+13
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* Merge pull request #659 from litghost/pseudo_pip_fixesgatecat2021-04-0611-66/+882
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| * [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
| * Don't fail-fast for GH actions to allow for easier CI debugging.Keith Rothman2021-04-061-0/+3
| * [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-063-6/+7
| * [interchange] Fix invalid use of local variables due to refactoring.Keith Rothman2021-04-063-6/+7
| * [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-063-42/+102
| * [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-062-5/+12
| * [interchange] Fix missing inline methods in site_arch.impl.hKeith Rothman2021-04-062-8/+9
| * [interchange] Disallow site edges during general routing.Keith Rothman2021-04-062-5/+23
| * [interchange] Add crude pseudo pip model.Keith Rothman2021-04-066-7/+717
* | Merge pull request #663 from litghost/fix_router2_without_bbgatecat2021-04-061-1/+13
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| * Fix bug in router2 where router may give up too early.Keith Rothman2021-04-061-1/+13
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