diff options
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/arch.h | 10 | ||||
| -rw-r--r-- | ice40/bitstream.cc | 10 |
2 files changed, 17 insertions, 3 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index 3563baad..5ed2347d 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -680,6 +680,16 @@ struct Arch : BaseArch<ArchRanges> return switches_locked[pi.switch_index] == WireId(); } + bool checkPipAvailForNet(PipId pip, NetInfo *net) const override + { + if (ice40_pip_hard_unavail(pip)) + return false; + + auto &pi = chip_info->pip_data[pip.index]; + auto swl = switches_locked[pi.switch_index]; + return swl == WireId() || (swl == getPipDstWire(pip) && wire_to_net[swl.index] == net); + } + NetInfo *getBoundPipNet(PipId pip) const override { NPNR_ASSERT(pip != PipId()); diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 3e50c065..2e1a6d4e 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -620,9 +620,13 @@ void write_asc(const Context *ctx, std::ostream &out) bool negclk_w = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK_W); int write_mode = get_param_or_def(ctx, cell.second.get(), id_WRITE_MODE); int read_mode = get_param_or_def(ctx, cell.second.get(), id_READ_MODE); - set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); - set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); - + if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) { + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_r); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_w); + } else { + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); + } set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1); set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2); set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1); |