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-rw-r--r--ice40/arch.cc31
-rw-r--r--ice40/arch.h2
-rw-r--r--ice40/family.cmake162
-rw-r--r--ice40/pack.cc9
4 files changed, 121 insertions, 83 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc
index f6084e72..23a2130c 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -19,6 +19,7 @@
*/
#include <algorithm>
+#include <boost/iostreams/device/mapped_file.hpp>
#include <cmath>
#include "cells.h"
#include "gfx.h"
@@ -48,9 +49,37 @@ static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return
void load_chipdb();
#endif
+#if defined(EXTERNAL_CHIPDB_ROOT)
+const char *chipdb_blob_384 = nullptr;
+const char *chipdb_blob_1k = nullptr;
+const char *chipdb_blob_5k = nullptr;
+const char *chipdb_blob_8k = nullptr;
+
+boost::iostreams::mapped_file_source blob_files[4];
+
+const char *mmap_file(int index, const char *filename)
+{
+ try {
+ blob_files[index].open(filename);
+ if (!blob_files[index].is_open())
+ log_error("Unable to read chipdb %s\n", filename);
+ return (const char *)blob_files[index].data();
+ } catch (...) {
+ log_error("Unable to read chipdb %s\n", filename);
+ }
+}
+
+void load_chipdb()
+{
+ chipdb_blob_384 = mmap_file(0, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-384.bin");
+ chipdb_blob_1k = mmap_file(1, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-1k.bin");
+ chipdb_blob_5k = mmap_file(2, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-5k.bin");
+ chipdb_blob_8k = mmap_file(3, EXTERNAL_CHIPDB_ROOT "/ice40/chipdb-8k.bin");
+}
+#endif
Arch::Arch(ArchArgs args) : args(args)
{
-#if defined(_MSC_VER)
+#if defined(_MSC_VER) || defined(EXTERNAL_CHIPDB_ROOT)
load_chipdb();
#endif
diff --git a/ice40/arch.h b/ice40/arch.h
index 2dd6b06c..b25e3aee 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -244,7 +244,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
RelPtr<RelPtr<char>> tile_wire_names;
});
-#if defined(_MSC_VER)
+#if defined(_MSC_VER) || defined(EXTERNAL_CHIPDB_ROOT)
extern const char *chipdb_blob_384;
extern const char *chipdb_blob_1k;
extern const char *chipdb_blob_5k;
diff --git a/ice40/family.cmake b/ice40/family.cmake
index 0e1d36e6..877b27ee 100644
--- a/ice40/family.cmake
+++ b/ice40/family.cmake
@@ -1,84 +1,86 @@
-if(ICE40_HX1K_ONLY)
- set(devices 1k)
- foreach (target ${family_targets})
- target_compile_definitions(${target} PRIVATE ICE40_HX1K_ONLY=1)
- endforeach (target)
-else()
- set(devices 384 1k 5k 8k)
-endif()
+if (NOT EXTERNAL_CHIPDB)
+ if(ICE40_HX1K_ONLY)
+ set(devices 1k)
+ foreach (target ${family_targets})
+ target_compile_definitions(${target} PRIVATE ICE40_HX1K_ONLY=1)
+ endforeach (target)
+ else()
+ set(devices 384 1k 5k 8k)
+ endif()
-set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdb.py)
+ set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdb.py)
-set(ICEBOX_ROOT "/usr/local/share/icebox" CACHE STRING "icebox location root")
-file(MAKE_DIRECTORY ice40/chipdbs/)
-add_library(ice40_chipdb OBJECT ice40/chipdbs/)
-target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
-target_include_directories(ice40_chipdb PRIVATE ${family}/)
+ set(ICEBOX_ROOT "/usr/local/share/icebox" CACHE STRING "icebox location root")
+ file(MAKE_DIRECTORY ice40/chipdbs/)
+ add_library(ice40_chipdb OBJECT ice40/chipdbs/)
+ target_compile_definitions(ice40_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family})
+ target_include_directories(ice40_chipdb PRIVATE ${family}/)
-if (MSVC)
- target_sources(ice40_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/embed.cc)
- set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ice40/resources/chipdb.rc PROPERTIES LANGUAGE RC)
- foreach (dev ${devices})
- if (dev EQUAL "5k")
- set(OPT_FAST "")
- set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt)
- elseif(dev EQUAL "384")
- set(OPT_FAST "")
- set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt)
- else()
- set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt)
- set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt)
- endif()
- set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
- set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
- set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bin)
- set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/constids.inc)
- set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h)
- add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
- COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}
- DEPENDS ${DEV_CONSTIDS_INC} ${DEV_GFXH} ${DEV_TXT_DB} ${DB_PY}
- )
- add_custom_command(OUTPUT ${DEV_CC_DB}
- COMMAND bbasm ${DEV_CC_BBA_DB} ${DEV_CC_DB}
- DEPENDS bbasm ${DEV_CC_BBA_DB}
- )
- target_sources(ice40_chipdb PRIVATE ${DEV_CC_DB})
- set_source_files_properties(${DEV_CC_DB} PROPERTIES HEADER_FILE_ONLY TRUE)
- foreach (target ${family_targets})
- target_sources(${target} PRIVATE $<TARGET_OBJECTS:ice40_chipdb> ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/chipdb.rc)
- endforeach (target)
- endforeach (dev)
-else()
- target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w)
- foreach (dev ${devices})
- if (dev EQUAL "5k")
- set(OPT_FAST "")
- set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt)
- elseif(dev EQUAL "384")
- set(OPT_FAST "")
- set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt)
- else()
- set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt)
- set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt)
- endif()
- set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
- set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
- set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.cc)
- set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/constids.inc)
- set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h)
- add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
- COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new
- COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB}
- DEPENDS ${DEV_CONSTIDS_INC} ${DEV_GFXH} ${DEV_TXT_DB} ${DB_PY}
- )
- add_custom_command(OUTPUT ${DEV_CC_DB}
- COMMAND bbasm --c ${DEV_CC_BBA_DB} ${DEV_CC_DB}.new
- COMMAND mv ${DEV_CC_DB}.new ${DEV_CC_DB}
- DEPENDS bbasm ${DEV_CC_BBA_DB}
- )
- target_sources(ice40_chipdb PRIVATE ${DEV_CC_DB})
- foreach (target ${family_targets})
- target_sources(${target} PRIVATE $<TARGET_OBJECTS:ice40_chipdb>)
- endforeach (target)
- endforeach (dev)
+ if (MSVC)
+ target_sources(ice40_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/embed.cc)
+ set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ice40/resources/chipdb.rc PROPERTIES LANGUAGE RC)
+ foreach (dev ${devices})
+ if (dev EQUAL "5k")
+ set(OPT_FAST "")
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt)
+ elseif(dev EQUAL "384")
+ set(OPT_FAST "")
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt)
+ else()
+ set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt)
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt)
+ endif()
+ set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
+ set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
+ set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bin)
+ set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/constids.inc)
+ set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h)
+ add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
+ COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}
+ DEPENDS ${DEV_CONSTIDS_INC} ${DEV_GFXH} ${DEV_TXT_DB} ${DB_PY}
+ )
+ add_custom_command(OUTPUT ${DEV_CC_DB}
+ COMMAND bbasm ${DEV_CC_BBA_DB} ${DEV_CC_DB}
+ DEPENDS bbasm ${DEV_CC_BBA_DB}
+ )
+ target_sources(ice40_chipdb PRIVATE ${DEV_CC_DB})
+ set_source_files_properties(${DEV_CC_DB} PROPERTIES HEADER_FILE_ONLY TRUE)
+ foreach (target ${family_targets})
+ target_sources(${target} PRIVATE $<TARGET_OBJECTS:ice40_chipdb> ${CMAKE_CURRENT_SOURCE_DIR}/ice40/resource/chipdb.rc)
+ endforeach (target)
+ endforeach (dev)
+ else()
+ target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w)
+ foreach (dev ${devices})
+ if (dev EQUAL "5k")
+ set(OPT_FAST "")
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_up5k.txt)
+ elseif(dev EQUAL "384")
+ set(OPT_FAST "")
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp384.txt)
+ else()
+ set(OPT_FAST --fast ${ICEBOX_ROOT}/timings_hx${dev}.txt)
+ set(OPT_SLOW --slow ${ICEBOX_ROOT}/timings_lp${dev}.txt)
+ endif()
+ set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
+ set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
+ set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.cc)
+ set(DEV_CONSTIDS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/constids.inc)
+ set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h)
+ add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
+ COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -p ${DEV_CONSTIDS_INC} -g ${DEV_GFXH} ${OPT_FAST} ${OPT_SLOW} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new
+ COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB}
+ DEPENDS ${DEV_CONSTIDS_INC} ${DEV_GFXH} ${DEV_TXT_DB} ${DB_PY}
+ )
+ add_custom_command(OUTPUT ${DEV_CC_DB}
+ COMMAND bbasm --c ${DEV_CC_BBA_DB} ${DEV_CC_DB}.new
+ COMMAND mv ${DEV_CC_DB}.new ${DEV_CC_DB}
+ DEPENDS bbasm ${DEV_CC_BBA_DB}
+ )
+ target_sources(ice40_chipdb PRIVATE ${DEV_CC_DB})
+ foreach (target ${family_targets})
+ target_sources(${target} PRIVATE $<TARGET_OBJECTS:ice40_chipdb>)
+ endforeach (target)
+ endforeach (dev)
+ endif()
endif()
diff --git a/ice40/pack.cc b/ice40/pack.cc
index a86083b6..c22c4e8c 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -770,6 +770,8 @@ static void place_plls(Context *ctx)
io_cell->name.c_str(ctx));
if (pll_used_bels.count(found_bel)) {
CellInfo *conflict_cell = pll_used_bels.at(found_bel);
+ if (conflict_cell == ci)
+ continue;
log_error("PLL '%s' PACKAGEPIN forces it to BEL %s but BEL is already assigned to PLL '%s'\n",
ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx), conflict_cell->name.c_str(ctx));
}
@@ -1063,7 +1065,12 @@ static void pack_special(Context *ctx)
create_ice_cell(ctx, ctx->id("ICESTORM_PLL"), ci->name.str(ctx) + "_PLL");
packed->attrs[ctx->id("TYPE")] = ci->type.str(ctx);
packed_cells.insert(ci->name);
-
+ if (!is_sb_pll40_dual(ctx, ci)) {
+ // Remove second output, so a buffer isn't created for it, for these
+ // cell types with only one output
+ packed->ports.erase(ctx->id("PLLOUT_B"));
+ packed->ports.erase(ctx->id("PLLOUT_B_GLOBAL"));
+ }
for (auto attr : ci->attrs)
packed->attrs[attr.first] = attr.second;
for (auto param : ci->params)
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-06 11:13:56 +0000