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-rw-r--r--ice40/arch.cc2
-rw-r--r--ice40/arch.h8
2 files changed, 9 insertions, 1 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 786d8ba1..d1400a63 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -102,7 +102,7 @@ BelType Arch::belTypeFromId(IdString type) const
// -----------------------------------------------------------------------
-void IdString::initialize_arch(const BaseCtx *ctx)
+void IdString::initialize_arch(const IdStringDB *ctx)
{
#define X(t) initialize_add(ctx, #t, PIN_##t);
#include "portpins.inc"
diff --git a/ice40/arch.h b/ice40/arch.h
index 3b6d23dc..f00d7f8a 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -389,6 +389,7 @@ struct Arch : BaseCtx
bel_to_cell[bel.index] = cell;
cells[cell]->bel = bel;
cells[cell]->belStrength = strength;
+ refreshUiBel(bel);
}
void unbindBel(BelId bel)
@@ -398,6 +399,7 @@ struct Arch : BaseCtx
cells[bel_to_cell[bel.index]]->bel = BelId();
cells[bel_to_cell[bel.index]]->belStrength = STRENGTH_NONE;
bel_to_cell[bel.index] = IdString();
+ refreshUiBel(bel);
}
bool checkBelAvail(BelId bel) const
@@ -491,6 +493,7 @@ struct Arch : BaseCtx
wire_to_net[wire.index] = net;
nets[net]->wires[wire].pip = PipId();
nets[net]->wires[wire].strength = strength;
+ refreshUiWire(wire);
}
void unbindWire(WireId wire)
@@ -510,6 +513,7 @@ struct Arch : BaseCtx
net_wires.erase(it);
wire_to_net[wire.index] = IdString();
+ refreshUiWire(wire);
}
bool checkWireAvail(WireId wire) const
@@ -557,6 +561,8 @@ struct Arch : BaseCtx
wire_to_net[dst.index] = net;
nets[net]->wires[dst].pip = pip;
nets[net]->wires[dst].strength = strength;
+ refreshUiPip(pip);
+ refreshUiWire(dst);
}
void unbindPip(PipId pip)
@@ -573,6 +579,8 @@ struct Arch : BaseCtx
pip_to_net[pip.index] = IdString();
switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString();
+ refreshUiPip(pip);
+ refreshUiWire(dst);
}
bool checkPipAvail(PipId pip) const