diff options
Diffstat (limited to 'gowin')
-rw-r--r-- | gowin/arch.cc | 24 | ||||
-rw-r--r-- | gowin/arch.h | 2 | ||||
-rw-r--r-- | gowin/constids.inc | 9 | ||||
-rw-r--r-- | gowin/pack.cc | 60 |
4 files changed, 52 insertions, 43 deletions
diff --git a/gowin/arch.cc b/gowin/arch.cc index 07938326..b104013d 100644 --- a/gowin/arch.cc +++ b/gowin/arch.cc @@ -688,7 +688,7 @@ void Arch::read_cst(std::istream &in) insloc } cst_type; - settings.erase(id("cst")); + settings.erase(id_cst); while (!in.eof()) { std::getline(in, line); cst_type = ioloc; @@ -756,7 +756,7 @@ void Arch::read_cst(std::istream &in) } } } - settings[id("cst")] = 1; + settings[id_cst] = 1; } // Add all MUXes for the cell @@ -1455,13 +1455,13 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const bool Arch::place() { - std::string placer = str_or_default(settings, id("placer"), defaultPlacer); + std::string placer = str_or_default(settings, id_placer, defaultPlacer); bool retVal; if (placer == "heap") { bool have_iobuf_or_constr = false; for (auto &cell : cells) { CellInfo *ci = cell.second.get(); - if (ci->type == id("IOB") || ci->bel != BelId() || ci->attrs.count(id("BEL"))) { + if (ci->type == id_IOB || ci->bel != BelId() || ci->attrs.count(id_BEL)) { have_iobuf_or_constr = true; break; } @@ -1472,15 +1472,15 @@ bool Arch::place() retVal = placer1(getCtx(), Placer1Cfg(getCtx())); } else { PlacerHeapCfg cfg(getCtx()); - cfg.ioBufTypes.insert(id("IOB")); + cfg.ioBufTypes.insert(id_IOB); cfg.beta = 0.5; retVal = placer_heap(getCtx(), cfg); } - getCtx()->settings[getCtx()->id("place")] = 1; + getCtx()->settings[id_place] = 1; archInfoToAttributes(); } else if (placer == "sa") { retVal = placer1(getCtx(), Placer1Cfg(getCtx())); - getCtx()->settings[getCtx()->id("place")] = 1; + getCtx()->settings[id_place] = 1; archInfoToAttributes(); return retVal; } else { @@ -1497,7 +1497,7 @@ bool Arch::place() bool Arch::route() { - std::string router = str_or_default(settings, id("router"), defaultRouter); + std::string router = str_or_default(settings, id_router, defaultRouter); bool result; if (router == "router1") { result = router1(getCtx(), Router1Cfg(getCtx())); @@ -1507,7 +1507,7 @@ bool Arch::route() } else { log_error("Gowin architecture does not support router '%s'\n", router.c_str()); } - getCtx()->settings[getCtx()->id("route")] = 1; + getCtx()->settings[id_route] = 1; archInfoToAttributes(); return result; } @@ -1600,9 +1600,9 @@ void Arch::assignArchInfo() ci->is_slice = true; ci->ff_used = ci->params.at(id_FF_USED).as_bool(); ci->ff_type = id(ci->params.at(id_FF_TYPE).as_string()); - ci->slice_clk = get_net_or_empty(ci, id("CLK")); - ci->slice_ce = get_net_or_empty(ci, id("CE")); - ci->slice_lsr = get_net_or_empty(ci, id("LSR")); + ci->slice_clk = get_net_or_empty(ci, id_CLK); + ci->slice_ce = get_net_or_empty(ci, id_CE); + ci->slice_lsr = get_net_or_empty(ci, id_LSR); // add timing paths addCellTimingClock(cname, id_CLK); diff --git a/gowin/arch.h b/gowin/arch.h index 9ce3bd1c..7a5dfc46 100644 --- a/gowin/arch.h +++ b/gowin/arch.h @@ -354,7 +354,7 @@ struct Arch : BaseArch<ArchRanges> std::string getChipName() const override { return device; } ArchArgs archArgs() const override { return args; } - IdString archArgsToId(ArchArgs args) const override { return id("none"); } + IdString archArgsToId(ArchArgs args) const override { return id_none; } int getGridDimX() const override { return gridDimX; } int getGridDimY() const override { return gridDimY; } diff --git a/gowin/constids.inc b/gowin/constids.inc index 82d0bb11..be016e0e 100644 --- a/gowin/constids.inc +++ b/gowin/constids.inc @@ -806,3 +806,12 @@ X(DECAL_ALU_ACTIVE) + +X(SINGLE_INPUT_MUX) +X(cst) +X(none) +X(pack) +X(place) +X(placer) +X(route) +X(router) diff --git a/gowin/pack.cc b/gowin/pack.cc index 3d33f2d8..1201e310 100644 --- a/gowin/pack.cc +++ b/gowin/pack.cc @@ -114,7 +114,7 @@ static void pack_alus(Context *ctx) int alu_idx = 1; do { // go through the ALU chain - auto alu_bel = ci->attrs.find(ctx->id("BEL")); + auto alu_bel = ci->attrs.find(id_BEL); if (alu_bel != ci->attrs.end()) { log_error("ALU %s placement restrictions are not supported.\n", ctx->nameOf(ci)); return; @@ -243,7 +243,7 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce std::vector<std::unique_ptr<CellInfo>> &new_cells) { - if (bool_or_default(ci->attrs, ctx->id("SINGLE_INPUT_MUX"))) { + if (bool_or_default(ci->attrs, id_SINGLE_INPUT_MUX)) { // find the muxed LUT NetInfo *i1 = ci->ports.at(id_I1).net; @@ -257,14 +257,14 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce } // XXX enable the placement constraints - auto mux_bel = ci->attrs.find(ctx->id("BEL")); - auto lut1_bel = lut1->attrs.find(ctx->id("BEL")); + auto mux_bel = ci->attrs.find(id_BEL); + auto lut1_bel = lut1->attrs.find(id_BEL); if (lut1_bel != lut1->attrs.end() || mux_bel != ci->attrs.end()) { log_error("MUX2_LUT5 '%s' placement restrictions are not supported yet\n", ctx->nameOf(ci)); return; } - std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, ctx->id("GW_MUX2_LUT5"), ci->name.str(ctx) + "_LC"); + std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_GW_MUX2_LUT5, ci->name.str(ctx) + "_LC"); if (ctx->verbose) { log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get())); } @@ -299,15 +299,15 @@ static void pack_mux2_lut5(Context *ctx, CellInfo *ci, pool<IdString> &packed_ce } // XXX enable the placement constraints - auto mux_bel = ci->attrs.find(ctx->id("BEL")); - auto lut0_bel = lut0->attrs.find(ctx->id("BEL")); - auto lut1_bel = lut1->attrs.find(ctx->id("BEL")); + auto mux_bel = ci->attrs.find(id_BEL); + auto lut0_bel = lut0->attrs.find(id_BEL); + auto lut1_bel = lut1->attrs.find(id_BEL); if (lut0_bel != lut0->attrs.end() || lut1_bel != lut1->attrs.end() || mux_bel != ci->attrs.end()) { log_error("MUX2_LUT5 '%s' placement restrictions are not supported yet\n", ctx->nameOf(ci)); return; } - std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, ctx->id("GW_MUX2_LUT5"), ci->name.str(ctx) + "_LC"); + std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_GW_MUX2_LUT5, ci->name.str(ctx) + "_LC"); if (ctx->verbose) { log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get())); } @@ -354,9 +354,9 @@ static void pack_mux2_lut(Context *ctx, CellInfo *ci, bool (*pred)(const BaseCtx } // XXX enable the placement constraints - auto mux_bel = ci->attrs.find(ctx->id("BEL")); - auto mux0_bel = mux0->attrs.find(ctx->id("BEL")); - auto mux1_bel = mux1->attrs.find(ctx->id("BEL")); + auto mux_bel = ci->attrs.find(id_BEL); + auto mux0_bel = mux0->attrs.find(id_BEL); + auto mux1_bel = mux1->attrs.find(id_BEL); if (mux0_bel != mux0->attrs.end() || mux1_bel != mux1->attrs.end() || mux_bel != ci->attrs.end()) { log_error("MUX2_LUT%c '%s' placement restrictions are not supported yet\n", type_suffix, ctx->nameOf(ci)); return; @@ -512,7 +512,7 @@ static void pack_lut_lutffs(Context *ctx) if (ctx->verbose) log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx)); if (is_lut(ctx, ci)) { - std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, ctx->id("SLICE"), ci->name.str(ctx) + "_LC"); + std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "_LC"); for (auto &attr : ci->attrs) packed->attrs[attr.first] = attr.second; packed_cells.insert(ci->name); @@ -520,14 +520,14 @@ static void pack_lut_lutffs(Context *ctx) log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get())); // See if we can pack into a DFF // TODO: LUT cascade - NetInfo *o = ci->ports.at(ctx->id("F")).net; - CellInfo *dff = net_only_drives(ctx, o, is_ff, ctx->id("D"), true); - auto lut_bel = ci->attrs.find(ctx->id("BEL")); + NetInfo *o = ci->ports.at(id_F).net; + CellInfo *dff = net_only_drives(ctx, o, is_ff, id_D, true); + auto lut_bel = ci->attrs.find(id_BEL); bool packed_dff = false; if (dff) { if (ctx->verbose) log_info("found attached dff %s\n", ctx->nameOf(dff)); - auto dff_bel = dff->attrs.find(ctx->id("BEL")); + auto dff_bel = dff->attrs.find(id_BEL); if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) { // Locations don't match, can't pack } else { @@ -535,7 +535,7 @@ static void pack_lut_lutffs(Context *ctx) dff_to_lc(ctx, dff, packed.get(), false); ctx->nets.erase(o->name); if (dff_bel != dff->attrs.end()) - packed->attrs[ctx->id("BEL")] = dff_bel->second; + packed->attrs[id_BEL] = dff_bel->second; packed_cells.insert(dff->name); if (ctx->verbose) log_info("packed cell %s into %s\n", ctx->nameOf(dff), ctx->nameOf(packed.get())); @@ -567,7 +567,7 @@ static void pack_nonlut_ffs(Context *ctx) for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); if (is_ff(ctx, ci)) { - std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, ctx->id("SLICE"), ci->name.str(ctx) + "_DFFLC"); + std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "_DFFLC"); for (auto &attr : ci->attrs) packed->attrs[attr.first] = attr.second; if (ctx->verbose) @@ -610,20 +610,20 @@ static void pack_constants(Context *ctx) { log_info("Packing constants..\n"); - std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, ctx->id("SLICE"), "$PACKER_GND"); - gnd_cell->params[ctx->id("INIT")] = Property(0, 1 << 4); + std::unique_ptr<CellInfo> gnd_cell = create_generic_cell(ctx, id_SLICE, "$PACKER_GND"); + gnd_cell->params[id_INIT] = Property(0, 1 << 4); auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET")); gnd_net->driver.cell = gnd_cell.get(); - gnd_net->driver.port = ctx->id("F"); - gnd_cell->ports.at(ctx->id("F")).net = gnd_net.get(); + gnd_net->driver.port = id_F; + gnd_cell->ports.at(id_F).net = gnd_net.get(); - std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, ctx->id("SLICE"), "$PACKER_VCC"); + std::unique_ptr<CellInfo> vcc_cell = create_generic_cell(ctx, id_SLICE, "$PACKER_VCC"); // Fill with 1s - vcc_cell->params[ctx->id("INIT")] = Property(Property::S1).extract(0, (1 << 4), Property::S1); + vcc_cell->params[id_INIT] = Property(Property::S1).extract(0, (1 << 4), Property::S1); auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET")); vcc_net->driver.cell = vcc_cell.get(); - vcc_net->driver.port = ctx->id("F"); - vcc_cell->ports.at(ctx->id("F")).net = vcc_net.get(); + vcc_net->driver.port = id_F; + vcc_cell->ports.at(id_F).net = vcc_net.get(); std::vector<IdString> dead_nets; @@ -631,13 +631,13 @@ static void pack_constants(Context *ctx) for (auto &net : ctx->nets) { NetInfo *ni = net.second.get(); - if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) { + if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) { IdString drv_cell = ni->driver.cell->name; set_net_constant(ctx, ni, gnd_net.get(), false); gnd_used = true; dead_nets.push_back(net.first); ctx->cells.erase(drv_cell); - } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) { + } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) { IdString drv_cell = ni->driver.cell->name; set_net_constant(ctx, ni, vcc_net.get(), true); dead_nets.push_back(net.first); @@ -780,7 +780,7 @@ bool Arch::pack() pack_alus(ctx); pack_lut_lutffs(ctx); pack_nonlut_ffs(ctx); - ctx->settings[ctx->id("pack")] = 1; + ctx->settings[id_pack] = 1; ctx->assignArchInfo(); log_info("Checksum: 0x%08x\n", ctx->checksum()); return true; |