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-rw-r--r--generic/arch.cc333
-rw-r--r--generic/arch.h113
-rw-r--r--generic/arch_pybindings.cc64
-rw-r--r--generic/arch_pybindings.h67
-rw-r--r--generic/archdefs.h44
-rw-r--r--generic/examples/write_fasm.py2
-rw-r--r--generic/family.cmake7
-rw-r--r--generic/main.cc15
-rw-r--r--generic/pack.cc14
-rw-r--r--generic/viaduct/example/.gitignore1
-rw-r--r--generic/viaduct/example/constids.inc14
-rw-r--r--generic/viaduct/example/example.cc306
-rw-r--r--generic/viaduct/example/example_map.v12
-rw-r--r--generic/viaduct/example/example_prims.v35
-rw-r--r--generic/viaduct/example/synth_viaduct_example.tcl24
-rwxr-xr-xgeneric/viaduct/example/viaduct_example.sh6
-rw-r--r--generic/viaduct_api.cc118
-rw-r--r--generic/viaduct_api.h114
-rw-r--r--generic/viaduct_constids.h74
-rw-r--r--generic/viaduct_helpers.cc163
-rw-r--r--generic/viaduct_helpers.h82
21 files changed, 1375 insertions, 233 deletions
diff --git a/generic/arch.cc b/generic/arch.cc
index ebc1ef26..ad054efd 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -25,49 +25,31 @@
#include "router1.h"
#include "router2.h"
#include "util.h"
+#include "viaduct_api.h"
NEXTPNR_NAMESPACE_BEGIN
-WireInfo &Arch::wire_info(IdStringList wire)
+WireId Arch::addWire(IdStringList name, IdString type, int x, int y)
{
- auto w = wires.find(wire);
- if (w == wires.end())
- NPNR_ASSERT_FALSE_STR("no wire named " + wire.str(getCtx()));
- return w->second;
-}
-
-PipInfo &Arch::pip_info(IdStringList pip)
-{
- auto p = pips.find(pip);
- if (p == pips.end())
- NPNR_ASSERT_FALSE_STR("no pip named " + pip.str(getCtx()));
- return p->second;
-}
-
-BelInfo &Arch::bel_info(IdStringList bel)
-{
- auto b = bels.find(bel);
- if (b == bels.end())
- NPNR_ASSERT_FALSE_STR("no bel named " + bel.str(getCtx()));
- return b->second;
-}
-
-void Arch::addWire(IdStringList name, IdString type, int x, int y)
-{
- NPNR_ASSERT(wires.count(name) == 0);
- WireInfo &wi = wires[name];
+ NPNR_ASSERT(wire_by_name.count(name) == 0);
+ WireId wire(wires.size());
+ wire_by_name[name] = wire;
+ wires.emplace_back();
+ WireInfo &wi = wires.back();
wi.name = name;
wi.type = type;
wi.x = x;
wi.y = y;
-
- wire_ids.push_back(name);
+ return wire;
}
-void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, delay_t delay, Loc loc)
+PipId Arch::addPip(IdStringList name, IdString type, WireId srcWire, WireId dstWire, delay_t delay, Loc loc)
{
- NPNR_ASSERT(pips.count(name) == 0);
- PipInfo &pi = pips[name];
+ NPNR_ASSERT(pip_by_name.count(name) == 0);
+ PipId pip(pips.size());
+ pip_by_name[name] = pip;
+ pips.emplace_back();
+ PipInfo &pi = pips.back();
pi.name = name;
pi.type = type;
pi.srcWire = srcWire;
@@ -75,9 +57,8 @@ void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStri
pi.delay = delay;
pi.loc = loc;
- wire_info(srcWire).downhill.push_back(name);
- wire_info(dstWire).uphill.push_back(name);
- pip_ids.push_back(name);
+ wire_info(srcWire).downhill.push_back(pip);
+ wire_info(dstWire).uphill.push_back(pip);
if (int(tilePipDimZ.size()) <= loc.x)
tilePipDimZ.resize(loc.x + 1);
@@ -88,13 +69,17 @@ void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStri
gridDimX = std::max(gridDimX, loc.x + 1);
gridDimY = std::max(gridDimY, loc.x + 1);
tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
+ return pip;
}
-void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden)
+BelId Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden)
{
- NPNR_ASSERT(bels.count(name) == 0);
+ NPNR_ASSERT(bel_by_name.count(name) == 0);
NPNR_ASSERT(bel_by_loc.count(loc) == 0);
- BelInfo &bi = bels[name];
+ BelId bel(bels.size());
+ bel_by_name[name] = bel;
+ bels.emplace_back();
+ BelInfo &bi = bels.back();
bi.name = name;
bi.type = type;
bi.x = loc.x;
@@ -103,8 +88,7 @@ void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidde
bi.gb = gb;
bi.hidden = hidden;
- bel_ids.push_back(name);
- bel_by_loc[loc] = name;
+ bel_by_loc[loc] = bel;
if (int(bels_by_tile.size()) <= loc.x)
bels_by_tile.resize(loc.x + 1);
@@ -112,7 +96,7 @@ void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidde
if (int(bels_by_tile[loc.x].size()) <= loc.y)
bels_by_tile[loc.x].resize(loc.y + 1);
- bels_by_tile[loc.x][loc.y].push_back(name);
+ bels_by_tile[loc.x][loc.y].push_back(bel);
if (int(tileBelDimZ.size()) <= loc.x)
tileBelDimZ.resize(loc.x + 1);
@@ -123,49 +107,50 @@ void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidde
gridDimX = std::max(gridDimX, loc.x + 1);
gridDimY = std::max(gridDimY, loc.x + 1);
tileBelDimZ[loc.x][loc.y] = std::max(tileBelDimZ[loc.x][loc.y], loc.z + 1);
+ return bel;
}
-void Arch::addBelInput(IdStringList bel, IdString name, IdStringList wire)
+void Arch::addBelInput(BelId bel, IdString name, WireId wire)
{
- NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
- PinInfo &pi = bel_info(bel).pins[name];
+ auto &bi = bel_info(bel);
+ NPNR_ASSERT(bi.pins.count(name) == 0);
+ PinInfo &pi = bi.pins[name];
pi.name = name;
pi.wire = wire;
pi.type = PORT_IN;
- wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
}
-void Arch::addBelOutput(IdStringList bel, IdString name, IdStringList wire)
+void Arch::addBelOutput(BelId bel, IdString name, WireId wire)
{
- NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
- PinInfo &pi = bel_info(bel).pins[name];
+ auto &bi = bel_info(bel);
+ NPNR_ASSERT(bi.pins.count(name) == 0);
+ PinInfo &pi = bi.pins[name];
pi.name = name;
pi.wire = wire;
pi.type = PORT_OUT;
- wire_info(wire).uphill_bel_pin = BelPin{bel, name};
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
}
-void Arch::addBelInout(IdStringList bel, IdString name, IdStringList wire)
+void Arch::addBelInout(BelId bel, IdString name, WireId wire)
{
- NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
- PinInfo &pi = bel_info(bel).pins[name];
+ auto &bi = bel_info(bel);
+ NPNR_ASSERT(bi.pins.count(name) == 0);
+ PinInfo &pi = bi.pins[name];
pi.name = name;
pi.wire = wire;
pi.type = PORT_INOUT;
- wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
wire_info(wire).bel_pins.push_back(BelPin{bel, name});
}
-void Arch::addGroupBel(IdStringList group, IdStringList bel) { groups[group].bels.push_back(bel); }
+void Arch::addGroupBel(IdStringList group, BelId bel) { groups[group].bels.push_back(bel); }
-void Arch::addGroupWire(IdStringList group, IdStringList wire) { groups[group].wires.push_back(wire); }
+void Arch::addGroupWire(IdStringList group, WireId wire) { groups[group].wires.push_back(wire); }
-void Arch::addGroupPip(IdStringList group, IdStringList pip) { groups[group].pips.push_back(pip); }
+void Arch::addGroupPip(IdStringList group, PipId pip) { groups[group].pips.push_back(pip); }
void Arch::addGroupGroup(IdStringList group, IdStringList grp) { groups[group].groups.push_back(grp); }
@@ -177,19 +162,19 @@ void Arch::addDecalGraphic(DecalId decal, const GraphicElement &graphic)
void Arch::setWireDecal(WireId wire, DecalXY decalxy)
{
- wire_info(wire).decalxy = decalxy;
+ wires.at(wire.index).decalxy = decalxy;
refreshUiWire(wire);
}
void Arch::setPipDecal(PipId pip, DecalXY decalxy)
{
- pip_info(pip).decalxy = decalxy;
+ pips.at(pip.index).decalxy = decalxy;
refreshUiPip(pip);
}
void Arch::setBelDecal(BelId bel, DecalXY decalxy)
{
- bel_info(bel).decalxy = decalxy;
+ bels.at(bel.index).decalxy = decalxy;
refreshUiBel(bel);
}
@@ -199,14 +184,11 @@ void Arch::setGroupDecal(GroupId group, DecalXY decalxy)
refreshUiGroup(group);
}
-void Arch::setWireAttr(IdStringList wire, IdString key, const std::string &value)
-{
- wire_info(wire).attrs[key] = value;
-}
+void Arch::setWireAttr(WireId wire, IdString key, const std::string &value) { wire_info(wire).attrs[key] = value; }
-void Arch::setPipAttr(IdStringList pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; }
+void Arch::setPipAttr(PipId pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; }
-void Arch::setBelAttr(IdStringList bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; }
+void Arch::setBelAttr(BelId bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; }
void Arch::setLutK(int K) { args.K = K; }
@@ -268,16 +250,19 @@ void IdString::initialize_arch(const BaseCtx *ctx) {}
BelId Arch::getBelByName(IdStringList name) const
{
- if (bels.count(name))
- return name;
- return BelId();
+ if (name.size() == 0)
+ return BelId();
+ auto fnd = bel_by_name.find(name);
+ if (fnd == bel_by_name.end())
+ NPNR_ASSERT_FALSE_STR("no bel named " + name.str(getCtx()));
+ return fnd->second;
}
-IdStringList Arch::getBelName(BelId bel) const { return bel; }
+IdStringList Arch::getBelName(BelId bel) const { return bel_info(bel).name; }
Loc Arch::getBelLocation(BelId bel) const
{
- auto &info = bels.at(bel);
+ auto &info = bel_info(bel);
return Loc(info.x, info.y, info.z);
}
@@ -291,7 +276,7 @@ BelId Arch::getBelByLocation(Loc loc) const
const std::vector<BelId> &Arch::getBelsByTile(int x, int y) const { return bels_by_tile.at(x).at(y); }
-bool Arch::getBelGlobalBuf(BelId bel) const { return bels.at(bel).gb; }
+bool Arch::getBelGlobalBuf(BelId bel) const { return bel_info(bel).gb; }
uint32_t Arch::getBelChecksum(BelId bel) const
{
@@ -301,7 +286,9 @@ uint32_t Arch::getBelChecksum(BelId bel) const
void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
{
- bels.at(bel).bound_cell = cell;
+ if (uarch)
+ uarch->notifyBelChange(bel, cell);
+ bel_info(bel).bound_cell = cell;
cell->bel = bel;
cell->belStrength = strength;
refreshUiBel(bel);
@@ -309,40 +296,46 @@ void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
void Arch::unbindBel(BelId bel)
{
- bels.at(bel).bound_cell->bel = BelId();
- bels.at(bel).bound_cell->belStrength = STRENGTH_NONE;
- bels.at(bel).bound_cell = nullptr;
+ if (uarch)
+ uarch->notifyBelChange(bel, nullptr);
+ auto &bi = bel_info(bel);
+ bi.bound_cell->bel = BelId();
+ bi.bound_cell->belStrength = STRENGTH_NONE;
+ bi.bound_cell = nullptr;
refreshUiBel(bel);
}
-bool Arch::checkBelAvail(BelId bel) const { return bels.at(bel).bound_cell == nullptr; }
+bool Arch::checkBelAvail(BelId bel) const
+{
+ return (!uarch || uarch->checkBelAvail(bel)) && (bel_info(bel).bound_cell == nullptr);
+}
-CellInfo *Arch::getBoundBelCell(BelId bel) const { return bels.at(bel).bound_cell; }
+CellInfo *Arch::getBoundBelCell(BelId bel) const { return bel_info(bel).bound_cell; }
-CellInfo *Arch::getConflictingBelCell(BelId bel) const { return bels.at(bel).bound_cell; }
+CellInfo *Arch::getConflictingBelCell(BelId bel) const { return bel_info(bel).bound_cell; }
-const std::vector<BelId> &Arch::getBels() const { return bel_ids; }
+linear_range<BelId> Arch::getBels() const { return linear_range<BelId>(bels.size()); }
-IdString Arch::getBelType(BelId bel) const { return bels.at(bel).type; }
+IdString Arch::getBelType(BelId bel) const { return bel_info(bel).type; }
-bool Arch::getBelHidden(BelId bel) const { return bels.at(bel).hidden; }
+bool Arch::getBelHidden(BelId bel) const { return bel_info(bel).hidden; }
-const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bels.at(bel).attrs; }
+const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bel_info(bel).attrs; }
WireId Arch::getBelPinWire(BelId bel, IdString pin) const
{
- const auto &bdata = bels.at(bel);
+ const auto &bdata = bel_info(bel);
if (!bdata.pins.count(pin))
log_error("bel '%s' has no pin '%s'\n", getCtx()->nameOfBel(bel), pin.c_str(this));
return bdata.pins.at(pin).wire;
}
-PortType Arch::getBelPinType(BelId bel, IdString pin) const { return bels.at(bel).pins.at(pin).type; }
+PortType Arch::getBelPinType(BelId bel, IdString pin) const { return bel_info(bel).pins.at(pin).type; }
std::vector<IdString> Arch::getBelPins(BelId bel) const
{
std::vector<IdString> ret;
- for (auto &it : bels.at(bel).pins)
+ for (auto &it : bel_info(bel).pins)
ret.push_back(it.first);
return ret;
}
@@ -356,26 +349,27 @@ const std::vector<IdString> &Arch::getBelPinsForCellPin(const CellInfo *cell_inf
WireId Arch::getWireByName(IdStringList name) const
{
- if (wires.count(name))
- return name;
- return WireId();
+ if (name.size() == 0)
+ return WireId();
+ auto fnd = wire_by_name.find(name);
+ if (fnd == wire_by_name.end())
+ NPNR_ASSERT_FALSE_STR("no wire named " + name.str(getCtx()));
+ return fnd->second;
}
-IdStringList Arch::getWireName(WireId wire) const { return wire; }
+IdStringList Arch::getWireName(WireId wire) const { return wire_info(wire).name; }
-IdString Arch::getWireType(WireId wire) const { return wires.at(wire).type; }
+IdString Arch::getWireType(WireId wire) const { return wire_info(wire).type; }
-const std::map<IdString, std::string> &Arch::getWireAttrs(WireId wire) const { return wires.at(wire).attrs; }
+const std::map<IdString, std::string> &Arch::getWireAttrs(WireId wire) const { return wire_info(wire).attrs; }
-uint32_t Arch::getWireChecksum(WireId wire) const
-{
- // FIXME
- return 0;
-}
+uint32_t Arch::getWireChecksum(WireId wire) const { return wire.index; }
void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
{
- wires.at(wire).bound_net = net;
+ if (uarch)
+ uarch->notifyWireChange(wire, net);
+ wire_info(wire).bound_net = net;
net->wires[wire].pip = PipId();
net->wires[wire].strength = strength;
refreshUiWire(wire);
@@ -383,55 +377,64 @@ void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
void Arch::unbindWire(WireId wire)
{
- auto &net_wires = wires.at(wire).bound_net->wires;
+ auto &net_wires = wire_info(wire).bound_net->wires;
auto pip = net_wires.at(wire).pip;
if (pip != PipId()) {
- pips.at(pip).bound_net = nullptr;
+ if (uarch)
+ uarch->notifyPipChange(pip, nullptr);
+ pip_info(pip).bound_net = nullptr;
refreshUiPip(pip);
}
+ uarch->notifyWireChange(wire, nullptr);
net_wires.erase(wire);
- wires.at(wire).bound_net = nullptr;
+ wire_info(wire).bound_net = nullptr;
refreshUiWire(wire);
}
-bool Arch::checkWireAvail(WireId wire) const { return wires.at(wire).bound_net == nullptr; }
+bool Arch::checkWireAvail(WireId wire) const
+{
+ return (!uarch || uarch->checkWireAvail(wire)) && (wire_info(wire).bound_net == nullptr);
+}
-NetInfo *Arch::getBoundWireNet(WireId wire) const { return wires.at(wire).bound_net; }
+NetInfo *Arch::getBoundWireNet(WireId wire) const { return wire_info(wire).bound_net; }
-NetInfo *Arch::getConflictingWireNet(WireId wire) const { return wires.at(wire).bound_net; }
+NetInfo *Arch::getConflictingWireNet(WireId wire) const { return wire_info(wire).bound_net; }
-const std::vector<BelPin> &Arch::getWireBelPins(WireId wire) const { return wires.at(wire).bel_pins; }
+const std::vector<BelPin> &Arch::getWireBelPins(WireId wire) const { return wire_info(wire).bel_pins; }
-const std::vector<WireId> &Arch::getWires() const { return wire_ids; }
+linear_range<WireId> Arch::getWires() const { return linear_range<WireId>(wires.size()); }
// ---------------------------------------------------------------
PipId Arch::getPipByName(IdStringList name) const
{
- if (pips.count(name))
- return name;
- return PipId();
+ if (name.size() == 0)
+ return PipId();
+ auto fnd = pip_by_name.find(name);
+ if (fnd == pip_by_name.end())
+ NPNR_ASSERT_FALSE_STR("no pip named " + name.str(getCtx()));
+ return fnd->second;
}
-IdStringList Arch::getPipName(PipId pip) const { return pip; }
+IdStringList Arch::getPipName(PipId pip) const { return pip_info(pip).name; }
-IdString Arch::getPipType(PipId pip) const { return pips.at(pip).type; }
+IdString Arch::getPipType(PipId pip) const { return pip_info(pip).type; }
-const std::map<IdString, std::string> &Arch::getPipAttrs(PipId pip) const { return pips.at(pip).attrs; }
+const std::map<IdString, std::string> &Arch::getPipAttrs(PipId pip) const { return pip_info(pip).attrs; }
-uint32_t Arch::getPipChecksum(PipId wire) const
-{
- // FIXME
- return 0;
-}
+uint32_t Arch::getPipChecksum(PipId pip) const { return pip.index; }
void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
{
- WireId wire = pips.at(pip).dstWire;
- pips.at(pip).bound_net = net;
- wires.at(wire).bound_net = net;
+ WireId wire = pip_info(pip).dstWire;
+ if (uarch) {
+ uarch->notifyPipChange(pip, net);
+ uarch->notifyWireChange(wire, net);
+ }
+ pip_info(pip).bound_net = net;
+ wire_info(wire).bound_net = net;
net->wires[wire].pip = pip;
net->wires[wire].strength = strength;
refreshUiPip(pip);
@@ -440,41 +443,53 @@ void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
void Arch::unbindPip(PipId pip)
{
- WireId wire = pips.at(pip).dstWire;
- wires.at(wire).bound_net->wires.erase(wire);
- pips.at(pip).bound_net = nullptr;
- wires.at(wire).bound_net = nullptr;
+ WireId wire = pip_info(pip).dstWire;
+ if (uarch) {
+ uarch->notifyPipChange(pip, nullptr);
+ uarch->notifyWireChange(wire, nullptr);
+ }
+ wire_info(wire).bound_net->wires.erase(wire);
+ pip_info(pip).bound_net = nullptr;
+ wire_info(wire).bound_net = nullptr;
refreshUiPip(pip);
refreshUiWire(wire);
}
-bool Arch::checkPipAvail(PipId pip) const { return pips.at(pip).bound_net == nullptr; }
+bool Arch::checkPipAvail(PipId pip) const
+{
+ return (!uarch || uarch->checkPipAvail(pip)) && (pip_info(pip).bound_net == nullptr);
+}
bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const
{
- NetInfo *bound_net = pips.at(pip).bound_net;
+ if (uarch && !uarch->checkPipAvailForNet(pip, net))
+ return false;
+ NetInfo *bound_net = pip_info(pip).bound_net;
return bound_net == nullptr || bound_net == net;
}
-NetInfo *Arch::getBoundPipNet(PipId pip) const { return pips.at(pip).bound_net; }
+NetInfo *Arch::getBoundPipNet(PipId pip) const { return pip_info(pip).bound_net; }
-NetInfo *Arch::getConflictingPipNet(PipId pip) const { return pips.at(pip).bound_net; }
+NetInfo *Arch::getConflictingPipNet(PipId pip) const { return pip_info(pip).bound_net; }
-WireId Arch::getConflictingPipWire(PipId pip) const { return pips.at(pip).bound_net ? pips.at(pip).dstWire : WireId(); }
+WireId Arch::getConflictingPipWire(PipId pip) const
+{
+ return pip_info(pip).bound_net ? pip_info(pip).dstWire : WireId();
+}
-const std::vector<PipId> &Arch::getPips() const { return pip_ids; }
+linear_range<PipId> Arch::getPips() const { return linear_range<PipId>(pips.size()); }
-Loc Arch::getPipLocation(PipId pip) const { return pips.at(pip).loc; }
+Loc Arch::getPipLocation(PipId pip) const { return pip_info(pip).loc; }
-WireId Arch::getPipSrcWire(PipId pip) const { return pips.at(pip).srcWire; }
+WireId Arch::getPipSrcWire(PipId pip) const { return pip_info(pip).srcWire; }
-WireId Arch::getPipDstWire(PipId pip) const { return pips.at(pip).dstWire; }
+WireId Arch::getPipDstWire(PipId pip) const { return pip_info(pip).dstWire; }
-DelayQuad Arch::getPipDelay(PipId pip) const { return DelayQuad(pips.at(pip).delay); }
+DelayQuad Arch::getPipDelay(PipId pip) const { return DelayQuad(pip_info(pip).delay); }
-const std::vector<PipId> &Arch::getPipsDownhill(WireId wire) const { return wires.at(wire).downhill; }
+const std::vector<PipId> &Arch::getPipsDownhill(WireId wire) const { return wire_info(wire).downhill; }
-const std::vector<PipId> &Arch::getPipsUphill(WireId wire) const { return wires.at(wire).uphill; }
+const std::vector<PipId> &Arch::getPipsUphill(WireId wire) const { return wire_info(wire).uphill; }
// ---------------------------------------------------------------
@@ -502,18 +517,21 @@ const std::vector<GroupId> &Arch::getGroupGroups(GroupId group) const { return g
delay_t Arch::estimateDelay(WireId src, WireId dst) const
{
- const WireInfo &s = wires.at(src);
- const WireInfo &d = wires.at(dst);
+ if (uarch)
+ return uarch->estimateDelay(src, dst);
+ const WireInfo &s = wire_info(src);
+ const WireInfo &d = wire_info(dst);
int dx = abs(s.x - d.x);
int dy = abs(s.y - d.y);
return (dx + dy) * args.delayScale + args.delayOffset;
}
-delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
+delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
{
- const auto &driver = net_info->driver;
- auto driver_loc = getBelLocation(driver.cell->bel);
- auto sink_loc = getBelLocation(sink.cell->bel);
+ if (uarch)
+ return uarch->predictDelay(src_bel, src_pin, dst_bel, dst_pin);
+ auto driver_loc = getBelLocation(src_bel);
+ auto sink_loc = getBelLocation(dst_bel);
int dx = abs(sink_loc.x - driver_loc.x);
int dy = abs(sink_loc.y - driver_loc.y);
@@ -524,12 +542,14 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
{
+ if (uarch)
+ return uarch->getRouteBoundingBox(src, dst);
ArcBounds bb;
- int src_x = wires.at(src).x;
- int src_y = wires.at(src).y;
- int dst_x = wires.at(dst).x;
- int dst_y = wires.at(dst).y;
+ int src_x = wire_info(src).x;
+ int src_y = wire_info(src).y;
+ int dst_x = wire_info(dst).x;
+ int dst_y = wire_info(dst).y;
bb.x0 = src_x;
bb.y0 = src_y;
@@ -550,6 +570,8 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
bool Arch::place()
{
+ if (uarch)
+ uarch->prePlace();
std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
if (placer == "heap") {
bool have_iobuf_or_constr = false;
@@ -561,7 +583,7 @@ bool Arch::place()
}
}
bool retVal;
- if (!have_iobuf_or_constr) {
+ if (!have_iobuf_or_constr && !uarch) {
log_warning("Unable to use HeAP due to a lack of IO buffers or constrained cells as anchors; reverting to "
"SA.\n");
retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
@@ -570,11 +592,15 @@ bool Arch::place()
cfg.ioBufTypes.insert(id("GENERIC_IOB"));
retVal = placer_heap(getCtx(), cfg);
}
+ if (uarch)
+ uarch->postPlace();
getCtx()->settings[getCtx()->id("place")] = 1;
archInfoToAttributes();
return retVal;
} else if (placer == "sa") {
bool retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
+ if (uarch)
+ uarch->postPlace();
getCtx()->settings[getCtx()->id("place")] = 1;
archInfoToAttributes();
return retVal;
@@ -585,6 +611,8 @@ bool Arch::place()
bool Arch::route()
{
+ if (uarch)
+ uarch->preRoute();
std::string router = str_or_default(settings, id("router"), defaultRouter);
bool result;
if (router == "router1") {
@@ -595,6 +623,8 @@ bool Arch::route()
} else {
log_error("iCE40 architecture does not support router '%s'\n", router.c_str());
}
+ if (uarch)
+ uarch->postRoute();
getCtx()->settings[getCtx()->id("route")] = 1;
archInfoToAttributes();
return result;
@@ -610,11 +640,11 @@ const std::vector<GraphicElement> &Arch::getDecalGraphics(DecalId decal) const
return decal_graphics.at(decal);
}
-DecalXY Arch::getBelDecal(BelId bel) const { return bels.at(bel).decalxy; }
+DecalXY Arch::getBelDecal(BelId bel) const { return bel_info(bel).decalxy; }
-DecalXY Arch::getWireDecal(WireId wire) const { return wires.at(wire).decalxy; }
+DecalXY Arch::getWireDecal(WireId wire) const { return wire_info(wire).decalxy; }
-DecalXY Arch::getPipDecal(PipId pip) const { return pips.at(pip).decalxy; }
+DecalXY Arch::getPipDecal(PipId pip) const { return pip_info(pip).decalxy; }
DecalXY Arch::getGroupDecal(GroupId group) const { return groups.at(group).decalxy; }
@@ -657,6 +687,8 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
bool Arch::isBelLocationValid(BelId bel) const
{
+ if (uarch)
+ return uarch->isBelLocationValid(bel);
std::vector<const CellInfo *> cells;
Loc loc = getBelLocation(bel);
for (auto tbel : getBelsByTile(loc.x, loc.y)) {
@@ -684,6 +716,7 @@ const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
void Arch::assignArchInfo()
{
+ int index = 0;
for (auto &cell : getCtx()->cells) {
CellInfo *ci = cell.second.get();
if (ci->type == id("GENERIC_SLICE")) {
@@ -697,6 +730,8 @@ void Arch::assignArchInfo()
for (auto &p : ci->ports)
if (!ci->bel_pins.count(p.first))
ci->bel_pins.emplace(p.first, std::vector<IdString>{p.first});
+ ci->flat_index = index;
+ ++index;
}
}
diff --git a/generic/arch.h b/generic/arch.h
index 2344d8b2..e96853f1 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -23,10 +23,12 @@
#include <map>
#include "arch_api.h"
+#include "base_arch.h"
#include "idstring.h"
#include "idstringlist.h"
#include "nextpnr_namespaces.h"
#include "nextpnr_types.h"
+#include "viaduct_api.h"
NEXTPNR_NAMESPACE_BEGIN
@@ -60,8 +62,6 @@ struct WireInfo
std::map<IdString, std::string> attrs;
NetInfo *bound_net;
std::vector<PipId> downhill, uphill;
- BelPin uphill_bel_pin;
- std::vector<BelPin> downhill_bel_pins;
std::vector<BelPin> bel_pins;
DecalXY decalxy;
int x, y;
@@ -111,23 +111,40 @@ struct CellTiming
dict<IdString, std::vector<TimingClockingInfo>> clockingInfo;
};
-struct ArchRanges
+template <typename TId> struct linear_range
+{
+ struct iterator
+ {
+ explicit iterator(int32_t index) : index(index){};
+ int32_t index;
+ bool operator==(const iterator &other) const { return index == other.index; }
+ bool operator!=(const iterator &other) const { return index != other.index; }
+ void operator++() { ++index; }
+ TId operator*() const { return TId(index); }
+ };
+ explicit linear_range(int32_t size) : size(size){};
+ int32_t size;
+ iterator begin() const { return iterator(0); }
+ iterator end() const { return iterator(size); }
+};
+
+struct ArchRanges : BaseArchRanges
{
using ArchArgsT = ArchArgs;
// Bels
- using AllBelsRangeT = const std::vector<BelId> &;
+ using AllBelsRangeT = linear_range<BelId>;
using TileBelsRangeT = const std::vector<BelId> &;
using BelAttrsRangeT = const std::map<IdString, std::string> &;
using BelPinsRangeT = std::vector<IdString>;
using CellBelPinRangeT = const std::vector<IdString> &;
// Wires
- using AllWiresRangeT = const std::vector<WireId> &;
+ using AllWiresRangeT = linear_range<WireId>;
using DownhillPipRangeT = const std::vector<PipId> &;
using UphillPipRangeT = const std::vector<PipId> &;
using WireBelPinRangeT = const std::vector<BelPin> &;
using WireAttrsRangeT = const std::map<IdString, std::string> &;
// Pips
- using AllPipsRangeT = const std::vector<PipId> &;
+ using AllPipsRangeT = linear_range<PipId>;
using PipAttrsRangeT = const std::map<IdString, std::string> &;
// Groups
using AllGroupsRangeT = std::vector<GroupId>;
@@ -143,21 +160,27 @@ struct ArchRanges
using BucketBelRangeT = std::vector<BelId>;
};
-struct Arch : ArchAPI<ArchRanges>
+struct Arch : BaseArch<ArchRanges>
{
std::string chipName;
+ std::unique_ptr<ViaductAPI> uarch{};
- dict<IdStringList, WireInfo> wires;
- dict<IdStringList, PipInfo> pips;
- dict<IdStringList, BelInfo> bels;
+ std::vector<WireInfo> wires;
+ std::vector<PipInfo> pips;
+ std::vector<BelInfo> bels;
dict<GroupId, GroupInfo> groups;
- // These functions include useful errors if not found
- WireInfo &wire_info(IdStringList wire);
- PipInfo &pip_info(IdStringList wire);
- BelInfo &bel_info(IdStringList wire);
+ WireInfo &wire_info(WireId wire) { return wires.at(wire.index); }
+ PipInfo &pip_info(PipId pip) { return pips.at(pip.index); }
+ BelInfo &bel_info(BelId bel) { return bels.at(bel.index); }
+
+ const WireInfo &wire_info(WireId wire) const { return wires.at(wire.index); }
+ const PipInfo &pip_info(PipId pip) const { return pips.at(pip.index); }
+ const BelInfo &bel_info(BelId bel) const { return bels.at(bel.index); }
- std::vector<IdStringList> bel_ids, wire_ids, pip_ids;
+ dict<IdStringList, WireId> wire_by_name;
+ dict<IdStringList, PipId> pip_by_name;
+ dict<IdStringList, BelId> bel_by_name;
dict<Loc, BelId> bel_by_loc;
std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
@@ -170,17 +193,17 @@ struct Arch : ArchAPI<ArchRanges>
dict<IdString, CellTiming> cellTiming;
- void addWire(IdStringList name, IdString type, int x, int y);
- void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, delay_t delay, Loc loc);
+ WireId addWire(IdStringList name, IdString type, int x, int y);
+ PipId addPip(IdStringList name, IdString type, WireId srcWire, WireId dstWire, delay_t delay, Loc loc);
- void addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
- void addBelInput(IdStringList bel, IdString name, IdStringList wire);
- void addBelOutput(IdStringList bel, IdString name, IdStringList wire);
- void addBelInout(IdStringList bel, IdString name, IdStringList wire);
+ BelId addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
+ void addBelInput(BelId bel, IdString name, WireId wire);
+ void addBelOutput(BelId bel, IdString name, WireId wire);
+ void addBelInout(BelId bel, IdString name, WireId wire);
- void addGroupBel(IdStringList group, IdStringList bel);
- void addGroupWire(IdStringList group, IdStringList wire);
- void addGroupPip(IdStringList group, IdStringList pip);
+ void addGroupBel(IdStringList group, BelId bel);
+ void addGroupWire(IdStringList group, WireId wire);
+ void addGroupPip(IdStringList group, PipId pip);
void addGroupGroup(IdStringList group, IdStringList grp);
void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
@@ -189,9 +212,9 @@ struct Arch : ArchAPI<ArchRanges>
void setBelDecal(BelId bel, DecalXY decalxy);
void setGroupDecal(GroupId group, DecalXY decalxy);
- void setWireAttr(IdStringList wire, IdString key, const std::string &value);
- void setPipAttr(IdStringList pip, IdString key, const std::string &value);
- void setBelAttr(IdStringList bel, IdString key, const std::string &value);
+ void setWireAttr(WireId wire, IdString key, const std::string &value);
+ void setPipAttr(PipId pip, IdString key, const std::string &value);
+ void setBelAttr(BelId bel, IdString key, const std::string &value);
void setLutK(int K);
void setDelayScaling(double scale, double offset);
@@ -234,7 +257,7 @@ struct Arch : ArchAPI<ArchRanges>
bool checkBelAvail(BelId bel) const override;
CellInfo *getBoundBelCell(BelId bel) const override;
CellInfo *getConflictingBelCell(BelId bel) const override;
- const std::vector<BelId> &getBels() const override;
+ linear_range<BelId> getBels() const override;
IdString getBelType(BelId bel) const override;
bool getBelHidden(BelId bel) const override;
const std::map<IdString, std::string> &getBelAttrs(BelId bel) const override;
@@ -255,7 +278,7 @@ struct Arch : ArchAPI<ArchRanges>
WireId getConflictingWireWire(WireId wire) const override { return wire; }
NetInfo *getConflictingWireNet(WireId wire) const override;
DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
- const std::vector<WireId> &getWires() const override;
+ linear_range<WireId> getWires() const override;
const std::vector<BelPin> &getWireBelPins(WireId wire) const override;
PipId getPipByName(IdStringList name) const override;
@@ -270,7 +293,7 @@ struct Arch : ArchAPI<ArchRanges>
NetInfo *getBoundPipNet(PipId pip) const override;
WireId getConflictingPipWire(PipId pip) const override;
NetInfo *getConflictingPipNet(PipId pip) const override;
- const std::vector<PipId> &getPips() const override;
+ linear_range<PipId> getPips() const override;
Loc getPipLocation(PipId pip) const override;
WireId getPipSrcWire(PipId pip) const override;
WireId getPipDstWire(PipId pip) const override;
@@ -287,7 +310,7 @@ struct Arch : ArchAPI<ArchRanges>
const std::vector<GroupId> &getGroupGroups(GroupId group) const override;
delay_t estimateDelay(WireId src, WireId dst) const override;
- delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
+ delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
delay_t getDelayEpsilon() const override { return 0.001; }
delay_t getRipupDelayPenalty() const override { return 0.015; }
float getDelayNS(delay_t v) const override { return v; }
@@ -305,9 +328,11 @@ struct Arch : ArchAPI<ArchRanges>
std::vector<IdString> getCellTypes() const override
{
+ if (uarch)
+ return uarch->getCellTypes();
pool<IdString> cell_types;
for (auto bel : bels) {
- cell_types.insert(bel.second.type);
+ cell_types.insert(bel.type);
}
return std::vector<IdString>{cell_types.begin(), cell_types.end()};
@@ -319,9 +344,15 @@ struct Arch : ArchAPI<ArchRanges>
BelBucketId getBelBucketByName(IdString bucket) const override { return bucket; }
- BelBucketId getBelBucketForBel(BelId bel) const override { return getBelType(bel); }
+ BelBucketId getBelBucketForBel(BelId bel) const override
+ {
+ return uarch ? uarch->getBelBucketForBel(bel) : getBelType(bel);
+ }
- BelBucketId getBelBucketForCellType(IdString cell_type) const override { return cell_type; }
+ BelBucketId getBelBucketForCellType(IdString cell_type) const override
+ {
+ return uarch ? uarch->getBelBucketForCellType(cell_type) : cell_type;
+ }
std::vector<BelId> getBelsInBucket(BelBucketId bucket) const override
{
@@ -346,19 +377,11 @@ struct Arch : ArchAPI<ArchRanges>
// Get the TimingClockingInfo of a port
TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override;
- bool isValidBelForCellType(IdString cell_type, BelId bel) const override { return cell_type == getBelType(bel); }
- bool isBelLocationValid(BelId bel) const override;
-
- // TODO
- CellInfo *getClusterRootCell(ClusterId cluster) const override { NPNR_ASSERT_FALSE("unimplemented"); }
- ArcBounds getClusterBounds(ClusterId cluster) const override { NPNR_ASSERT_FALSE("unimplemented"); }
- Loc getClusterOffset(const CellInfo *cell) const override { NPNR_ASSERT_FALSE("unimplemented"); }
- bool isClusterStrict(const CellInfo *cell) const override { NPNR_ASSERT_FALSE("unimplemented"); }
- bool getClusterPlacement(ClusterId cluster, BelId root_bel,
- std::vector<std::pair<CellInfo *, BelId>> &placement) const override
+ bool isValidBelForCellType(IdString cell_type, BelId bel) const override
{
- NPNR_ASSERT_FALSE("unimplemented");
+ return uarch ? uarch->isValidBelForCellType(cell_type, bel) : cell_type == getBelType(bel);
}
+ bool isBelLocationValid(BelId bel) const override;
static const std::string defaultPlacer;
static const std::vector<std::string> availablePlacers;
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index df59b4fe..92c78252 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -42,6 +42,10 @@ void arch_wrap_python(py::module &m)
{
using namespace PythonConversion;
+ typedef linear_range<BelId> BelRange;
+ typedef linear_range<WireId> WireRange;
+ typedef linear_range<PipId> AllPipRange;
+
auto arch_cls = py::class_<Arch, BaseCtx>(m, "Arch").def(py::init<ArchArgs>());
auto dxy_cls = py::class_<ContextualWrapper<DecalXY>>(m, "DecalXY_");
@@ -74,8 +78,8 @@ void arch_wrap_python(py::module &m)
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell");
fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell,
deref_and_wrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
- fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels,
- wrap_context<const std::vector<BelId> &>>::def_wrap(ctx_cls, "getBels");
+ fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, wrap_context<BelRange>>::def_wrap(ctx_cls,
+ "getBels");
fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
conv_from_str<BelId>, conv_from_str<IdString>>::def_wrap(ctx_cls, "getBelPinWire");
@@ -96,11 +100,11 @@ void arch_wrap_python(py::module &m)
fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet,
deref_and_wrap<NetInfo>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet");
- fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires,
- wrap_context<const std::vector<WireId> &>>::def_wrap(ctx_cls, "getWires");
+ fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires, wrap_context<WireRange>>::def_wrap(
+ ctx_cls, "getWires");
- fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips,
- wrap_context<const std::vector<PipId> &>>::def_wrap(ctx_cls, "getPips");
+ fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips, wrap_context<AllPipRange>>::def_wrap(
+ ctx_cls, "getPips");
fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>,
conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum");
fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>,
@@ -156,50 +160,50 @@ void arch_wrap_python(py::module &m)
"name"_a, "type"_a, "x"_a,
"y"_a);
fn_wrapper_6a_v<Context, decltype(&Context::addPip), &Context::addPip, conv_from_str<IdStringList>,
- conv_from_str<IdString>, conv_from_str<IdStringList>, conv_from_str<IdStringList>,
- pass_through<delay_t>, pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a,
- "srcWire"_a, "dstWire"_a, "delay"_a, "loc"_a);
+ conv_from_str<IdString>, conv_from_str<WireId>, conv_from_str<WireId>, pass_through<delay_t>,
+ pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a, "srcWire"_a, "dstWire"_a,
+ "delay"_a, "loc"_a);
fn_wrapper_5a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdStringList>,
conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>,
pass_through<bool>>::def_wrap(ctx_cls, "addBel", "name"_a, "type"_a, "loc"_a, "gb"_a, "hidden"_a);
- fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdStringList>,
- conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelInput", "bel"_a,
- "name"_a, "wire"_a);
- fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<IdStringList>,
- conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelOutput", "bel"_a,
- "name"_a, "wire"_a);
- fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<IdStringList>,
- conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelInout", "bel"_a,
- "name"_a, "wire"_a);
+ fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<BelId>,
+ conv_from_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "addBelInput", "bel"_a, "name"_a,
+ "wire"_a);
+ fn_wrapper_3a_v<Context, decltype(&Context::addBelOutput), &Context::addBelOutput, conv_from_str<BelId>,
+ conv_from_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "addBelOutput", "bel"_a,
+ "name"_a, "wire"_a);
+ fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<BelId>,
+ conv_from_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "addBelInout", "bel"_a, "name"_a,
+ "wire"_a);
fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdStringList>,
- conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);
+ conv_from_str<BelId>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);
fn_wrapper_2a_v<Context, decltype(&Context::addGroupWire), &Context::addGroupWire, conv_from_str<IdStringList>,
- conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupWire", "group"_a, "wire"_a);
+ conv_from_str<WireId>>::def_wrap(ctx_cls, "addGroupWire", "group"_a, "wire"_a);
fn_wrapper_2a_v<Context, decltype(&Context::addGroupPip), &Context::addGroupPip, conv_from_str<IdStringList>,
- conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupPip", "group"_a, "pip"_a);
- fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupPip, conv_from_str<IdStringList>,
+ conv_from_str<PipId>>::def_wrap(ctx_cls, "addGroupPip", "group"_a, "pip"_a);
+ fn_wrapper_2a_v<Context, decltype(&Context::addGroupGroup), &Context::addGroupGroup, conv_from_str<IdStringList>,
conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addGroupGroup", "group"_a, "grp"_a);
fn_wrapper_2a_v<Context, decltype(&Context::addDecalGraphic), &Context::addDecalGraphic, conv_from_str<DecalId>,
pass_through<GraphicElement>>::def_wrap(ctx_cls, "addDecalGraphic", (py::arg("decal"), "graphic"));
- fn_wrapper_2a_v<Context, decltype(&Context::setWireDecal), &Context::setWireDecal, conv_from_str<DecalId>,
+ fn_wrapper_2a_v<Context, decltype(&Context::setWireDecal), &Context::setWireDecal, conv_from_str<WireId>,
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setWireDecal", "wire"_a, "decalxy"_a);
- fn_wrapper_2a_v<Context, decltype(&Context::setPipDecal), &Context::setPipDecal, conv_from_str<DecalId>,
+ fn_wrapper_2a_v<Context, decltype(&Context::setPipDecal), &Context::setPipDecal, conv_from_str<PipId>,
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setPipDecal", "pip"_a, "decalxy"_a);
- fn_wrapper_2a_v<Context, decltype(&Context::setBelDecal), &Context::setBelDecal, conv_from_str<DecalId>,
+ fn_wrapper_2a_v<Context, decltype(&Context::setBelDecal), &Context::setBelDecal, conv_from_str<BelId>,
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setBelDecal", "bel"_a, "decalxy"_a);
fn_wrapper_2a_v<Context, decltype(&Context::setGroupDecal), &Context::setGroupDecal, conv_from_str<DecalId>,
unwrap_context<DecalXY>>::def_wrap(ctx_cls, "setGroupDecal", "group"_a, "decalxy"_a);
- fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<DecalId>,
+ fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<WireId>,
conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr", "wire"_a,
"key"_a, "value"_a);
- fn_wrapper_3a_v<Context, decltype(&Context::setBelAttr), &Context::setBelAttr, conv_from_str<DecalId>,
+ fn_wrapper_3a_v<Context, decltype(&Context::setBelAttr), &Context::setBelAttr, conv_from_str<BelId>,
conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setBelAttr", "bel"_a,
"key"_a, "value"_a);
- fn_wrapper_3a_v<Context, decltype(&Context::setPipAttr), &Context::setPipAttr, conv_from_str<DecalId>,
+ fn_wrapper_3a_v<Context, decltype(&Context::setPipAttr), &Context::setPipAttr, conv_from_str<PipId>,
conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setPipAttr", "pip"_a,
"key"_a, "value"_a);
@@ -254,6 +258,10 @@ void arch_wrap_python(py::module &m)
pass_through<bool>, conv_from_str<IdString>, conv_from_str<BelId>>::def_wrap(ctx_cls,
"isValidBelForCellType");
+ WRAP_RANGE(m, Bel, conv_to_str<BelId>);
+ WRAP_RANGE(m, Wire, conv_to_str<WireId>);
+ WRAP_RANGE(m, AllPip, conv_to_str<PipId>);
+
WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
diff --git a/generic/arch_pybindings.h b/generic/arch_pybindings.h
index 9a573540..72d688dc 100644
--- a/generic/arch_pybindings.h
+++ b/generic/arch_pybindings.h
@@ -26,6 +26,73 @@
NEXTPNR_NAMESPACE_BEGIN
+namespace PythonConversion {
+
+template <> struct string_converter<BelId>
+{
+ BelId from_str(Context *ctx, std::string name) { return ctx->getBelByNameStr(name); }
+
+ std::string to_str(Context *ctx, BelId id)
+ {
+ if (id == BelId())
+ throw bad_wrap();
+ return ctx->getBelName(id).str(ctx);
+ }
+};
+
+template <> struct string_converter<WireId>
+{
+ WireId from_str(Context *ctx, std::string name) { return ctx->getWireByNameStr(name); }
+
+ std::string to_str(Context *ctx, WireId id)
+ {
+ if (id == WireId())
+ throw bad_wrap();
+ return ctx->getWireName(id).str(ctx);
+ }
+};
+
+template <> struct string_converter<const WireId>
+{
+ WireId from_str(Context *ctx, std::string name) { return ctx->getWireByNameStr(name); }
+
+ std::string to_str(Context *ctx, WireId id)
+ {
+ if (id == WireId())
+ throw bad_wrap();
+ return ctx->getWireName(id).str(ctx);
+ }
+};
+
+template <> struct string_converter<PipId>
+{
+ PipId from_str(Context *ctx, std::string name) { return ctx->getPipByNameStr(name); }
+
+ std::string to_str(Context *ctx, PipId id)
+ {
+ if (id == PipId())
+ throw bad_wrap();
+ return ctx->getPipName(id).str(ctx);
+ }
+};
+
+template <> struct string_converter<BelPin>
+{
+ BelPin from_str(Context *ctx, std::string name)
+ {
+ NPNR_ASSERT_FALSE("string_converter<BelPin>::from_str not implemented");
+ }
+
+ std::string to_str(Context *ctx, BelPin pin)
+ {
+ if (pin.bel == BelId())
+ throw bad_wrap();
+ return ctx->getBelName(pin.bel).str(ctx) + "/" + pin.pin.str(ctx);
+ }
+};
+
+} // namespace PythonConversion
+
NEXTPNR_NAMESPACE_END
#endif
#endif
diff --git a/generic/archdefs.h b/generic/archdefs.h
index c46fba93..4e91ffd3 100644
--- a/generic/archdefs.h
+++ b/generic/archdefs.h
@@ -20,6 +20,7 @@
#ifndef GENERIC_ARCHDEFS_H
#define GENERIC_ARCHDEFS_H
+#include "base_clusterinfo.h"
#include "hashlib.h"
#include "idstringlist.h"
@@ -27,9 +28,42 @@ NEXTPNR_NAMESPACE_BEGIN
typedef float delay_t;
-typedef IdStringList BelId;
-typedef IdStringList WireId;
-typedef IdStringList PipId;
+struct BelId
+{
+ BelId() : index(-1){};
+ explicit BelId(int32_t index) : index(index){};
+ int32_t index = -1;
+
+ bool operator==(const BelId &other) const { return index == other.index; }
+ bool operator!=(const BelId &other) const { return index != other.index; }
+ bool operator<(const BelId &other) const { return index < other.index; }
+ unsigned int hash() const { return index; }
+};
+
+struct WireId
+{
+ WireId() : index(-1){};
+ explicit WireId(int32_t index) : index(index){};
+ int32_t index = -1;
+
+ bool operator==(const WireId &other) const { return index == other.index; }
+ bool operator!=(const WireId &other) const { return index != other.index; }
+ bool operator<(const WireId &other) const { return index < other.index; }
+ unsigned int hash() const { return index; }
+};
+
+struct PipId
+{
+ PipId() : index(-1){};
+ explicit PipId(int32_t index) : index(index){};
+ int32_t index = -1;
+
+ bool operator==(const PipId &other) const { return index == other.index; }
+ bool operator!=(const PipId &other) const { return index != other.index; }
+ bool operator<(const PipId &other) const { return index < other.index; }
+ unsigned int hash() const { return index; }
+};
+
typedef IdStringList GroupId;
typedef IdStringList DecalId;
typedef IdString BelBucketId;
@@ -41,7 +75,7 @@ struct ArchNetInfo
struct NetInfo;
-struct ArchCellInfo
+struct ArchCellInfo : BaseClusterInfo
{
// Custom grouping set via "PACK_GROUP" attribute. All cells with the same group
// value may share a tile (-1 = don't care, default if not set)
@@ -50,6 +84,8 @@ struct ArchCellInfo
bool is_slice;
// Only packing rule for slice type primitives is a single clock per tile
const NetInfo *slice_clk;
+ // A flat index for cells; so viaduct uarches can have their own fast flat arrays of per-cell validity-related data
+ int flat_index;
// Cell to bel pin mapping
dict<IdString, std::vector<IdString>> bel_pins;
};
diff --git a/generic/examples/write_fasm.py b/generic/examples/write_fasm.py
index ede8f16b..057e779c 100644
--- a/generic/examples/write_fasm.py
+++ b/generic/examples/write_fasm.py
@@ -29,7 +29,7 @@ def write_fasm(ctx, paramCfg, f):
for nname, net in sorted(ctx.nets, key=lambda x: str(x[1].name)):
print("# Net %s" % nname, file=f)
for wire, pip in sorted(net.wires, key=lambda x: str(x[1])):
- if pip.pip != "":
+ if pip.pip is not None:
print("%s" % pip.pip, file=f)
print("", file=f)
for cname, cell in sorted(ctx.cells, key=lambda x: str(x[1].name)):
diff --git a/generic/family.cmake b/generic/family.cmake
index e69de29b..cd4e3801 100644
--- a/generic/family.cmake
+++ b/generic/family.cmake
@@ -0,0 +1,7 @@
+set(VIADUCT_UARCHES "example")
+foreach(uarch ${VIADUCT_UARCHES})
+ aux_source_directory(${family}/viaduct/${uarch} UARCH_FILES)
+ foreach(target ${family_targets})
+ target_sources(${target} PRIVATE ${UARCH_FILES})
+ endforeach()
+endforeach(uarch)
diff --git a/generic/main.cc b/generic/main.cc
index 387df6c6..d08ae381 100644
--- a/generic/main.cc
+++ b/generic/main.cc
@@ -44,8 +44,10 @@ GenericCommandHandler::GenericCommandHandler(int argc, char **argv) : CommandHan
po::options_description GenericCommandHandler::getArchOptions()
{
+ std::string all_uarches = ViaductArch::list();
+ std::string uarch_help = stringf("viaduct micro-arch to use (available: %s)", all_uarches.c_str());
po::options_description specific("Architecture specific options");
- specific.add_options()("generic", "set device type to generic");
+ specific.add_options()("uarch", po::value<std::string>(), uarch_help.c_str());
specific.add_options()("no-iobs", "disable automatic IO buffer insertion");
return specific;
}
@@ -63,6 +65,17 @@ std::unique_ptr<Context> GenericCommandHandler::createContext(dict<std::string,
auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
if (vm.count("no-iobs"))
ctx->settings[ctx->id("disable_iobs")] = Property::State::S1;
+ if (vm.count("uarch")) {
+ std::string uarch_name = vm["uarch"].as<std::string>();
+ dict<std::string, std::string> args; // TODO
+ auto uarch = ViaductArch::create(uarch_name, args);
+ if (!uarch) {
+ std::string all_uarches = ViaductArch::list();
+ log_error("Unknown viaduct uarch '%s'; available options: '%s'\n", uarch_name.c_str(), all_uarches.c_str());
+ }
+ ctx->uarch = std::move(uarch);
+ ctx->uarch->init(ctx.get());
+ }
return ctx;
}
diff --git a/generic/pack.cc b/generic/pack.cc
index 32dae553..291a528d 100644
--- a/generic/pack.cc
+++ b/generic/pack.cc
@@ -276,12 +276,16 @@ bool Arch::pack()
Context *ctx = getCtx();
try {
log_break();
- pack_constants(ctx);
- pack_io(ctx);
- pack_lut_lutffs(ctx);
- pack_nonlut_ffs(ctx);
- ctx->settings[ctx->id("pack")] = 1;
+ if (uarch) {
+ uarch->pack();
+ } else {
+ pack_constants(ctx);
+ pack_io(ctx);
+ pack_lut_lutffs(ctx);
+ pack_nonlut_ffs(ctx);
+ }
ctx->assignArchInfo();
+ ctx->settings[ctx->id("pack")] = 1;
log_info("Checksum: 0x%08x\n", ctx->checksum());
return true;
} catch (log_execution_error_exception) {
diff --git a/generic/viaduct/example/.gitignore b/generic/viaduct/example/.gitignore
new file mode 100644
index 00000000..a6c57f5f
--- /dev/null
+++ b/generic/viaduct/example/.gitignore
@@ -0,0 +1 @@
+*.json
diff --git a/generic/viaduct/example/constids.inc b/generic/viaduct/example/constids.inc
new file mode 100644
index 00000000..b40d5be8
--- /dev/null
+++ b/generic/viaduct/example/constids.inc
@@ -0,0 +1,14 @@
+X(LUT4)
+X(DFF)
+X(CLK)
+X(D)
+X(F)
+X(Q)
+X(INBUF)
+X(OUTBUF)
+X(I)
+X(EN)
+X(O)
+X(IOB)
+X(PAD)
+X(INIT)
diff --git a/generic/viaduct/example/example.cc b/generic/viaduct/example/example.cc
new file mode 100644
index 00000000..3d1c201c
--- /dev/null
+++ b/generic/viaduct/example/example.cc
@@ -0,0 +1,306 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2021 gatecat <gatecat@ds0.me>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+#include "viaduct_api.h"
+#include "viaduct_helpers.h"
+
+#define GEN_INIT_CONSTIDS
+#define VIADUCT_CONSTIDS "viaduct/example/constids.inc"
+#include "viaduct_constids.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+struct ExampleImpl : ViaductAPI
+{
+ ~ExampleImpl(){};
+ void init(Context *ctx) override
+ {
+ init_uarch_constids(ctx);
+ ViaductAPI::init(ctx);
+ h.init(ctx);
+ init_wires();
+ init_bels();
+ init_pips();
+ }
+
+ void pack() override
+ {
+ // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
+ const pool<CellTypePort> top_ports{
+ CellTypePort(id_INBUF, id_PAD),
+ CellTypePort(id_OUTBUF, id_PAD),
+ };
+ h.remove_nextpnr_iobs(top_ports);
+ // Replace constants with LUTs
+ const dict<IdString, Property> vcc_params = {{id_INIT, Property(0xFFFF, 16)}};
+ const dict<IdString, Property> gnd_params = {{id_INIT, Property(0x0000, 16)}};
+ h.replace_constants(CellTypePort(id_LUT4, id_F), CellTypePort(id_LUT4, id_F), vcc_params, gnd_params);
+ // Constrain directly connected LUTs and FFs together to use dedicated resources
+ int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+ log_info("Constrained %d LUTFF pairs.\n", lutffs);
+ }
+
+ void prePlace() override { assign_cell_info(); }
+
+ bool isBelLocationValid(BelId bel) const override
+ {
+ Loc l = ctx->getBelLocation(bel);
+ if (is_io(l.x, l.y)) {
+ return true;
+ } else {
+ return slice_valid(l.x, l.y, l.z / 2);
+ }
+ }
+
+ private:
+ ViaductHelpers h;
+ // Configuration
+ // Grid size including IOBs at edges
+ const int X = 32, Y = 32;
+ // SLICEs per tile
+ const int N = 8;
+ // LUT input count
+ const int K = 4;
+ // Number of local wires
+ const int Wl = N * (K + 1) + 8;
+ // 1/Fc for bel input wire pips; local wire pips and neighbour pips
+ const int Si = 4, Sq = 4, Sl = 8;
+
+ // For fast wire lookups
+ struct TileWires
+ {
+ std::vector<WireId> clk, q, f, d, i;
+ std::vector<WireId> l;
+ std::vector<WireId> pad;
+ };
+
+ std::vector<std::vector<TileWires>> wires_by_tile;
+
+ // Create wires to attach to bels and pips
+ void init_wires()
+ {
+ log_info("Creating wires...\n");
+ wires_by_tile.resize(Y);
+ for (int y = 0; y < Y; y++) {
+ auto &row_wires = wires_by_tile.at(y);
+ row_wires.resize(X);
+ for (int x = 0; x < X; x++) {
+ auto &w = row_wires.at(x);
+ for (int z = 0; z < N; z++) {
+ // Clock input
+ w.clk.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("CLK%d", z))), ctx->id("CLK"), x, y));
+ // FF input
+ w.d.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("D%d", z))), ctx->id("D"), x, y));
+ // FF and LUT outputs
+ w.q.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("Q%d", z))), ctx->id("Q"), x, y));
+ w.f.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("F%d", z))), ctx->id("F"), x, y));
+ // LUT inputs
+ for (int i = 0; i < K; i++)
+ w.i.push_back(
+ ctx->addWire(h.xy_id(x, y, ctx->id(stringf("L%dI%d", z, i))), ctx->id("I"), x, y));
+ }
+ // Local wires
+ for (int l = 0; l < Wl; l++)
+ w.l.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("LOCAL%d", l))), ctx->id("LOCAL"), x, y));
+ // Pad wires for IO
+ if (is_io(x, y) && x != y)
+ for (int z = 0; z < 2; z++)
+ w.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->id(stringf("PAD%d", z))), id_PAD, x, y));
+ }
+ }
+ }
+ bool is_io(int x, int y) const
+ {
+ // IO are on the edges of the device
+ return (x == 0) || (x == (X - 1)) || (y == 0) || (y == (Y - 1));
+ }
+ // Create IO bels in an IO tile
+ void add_io_bels(int x, int y)
+ {
+ auto &w = wires_by_tile.at(y).at(x);
+ for (int z = 0; z < 2; z++) {
+ BelId b = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("IO%d", z))), id_IOB, Loc(x, y, z), false, false);
+ ctx->addBelInout(b, id_PAD, w.pad.at(z));
+ ctx->addBelInput(b, id_I, w.i.at(z * K + 0));
+ ctx->addBelInput(b, id_EN, w.i.at(z * K + 1));
+ ctx->addBelOutput(b, id_O, w.q.at(z));
+ }
+ }
+ PipId add_pip(Loc loc, WireId src, WireId dst, delay_t delay = 0.05)
+ {
+ IdStringList name = IdStringList::concat(ctx->getWireName(dst), ctx->getWireName(src));
+ return ctx->addPip(name, ctx->id("PIP"), src, dst, delay, loc);
+ }
+ // Create LUT and FF bels in a logic tile
+ void add_slice_bels(int x, int y)
+ {
+ auto &w = wires_by_tile.at(y).at(x);
+ for (int z = 0; z < N; z++) {
+ // Create LUT bel
+ BelId lut = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_LUT", z))), id_LUT4, Loc(x, y, z * 2), false,
+ false);
+ for (int k = 0; k < K; k++)
+ ctx->addBelInput(lut, ctx->id(stringf("I[%d]", k)), w.i.at(z * K + k));
+ ctx->addBelOutput(lut, id_F, w.f.at(z));
+ // FF data can come from LUT output or LUT I3
+ add_pip(Loc(x, y, 0), w.f.at(z), w.d.at(z));
+ add_pip(Loc(x, y, 0), w.i.at(z * K + (K - 1)), w.d.at(z));
+ // Create DFF bel
+ BelId dff = ctx->addBel(h.xy_id(x, y, ctx->id(stringf("SLICE%d_FF", z))), id_DFF, Loc(x, y, z * 2 + 1),
+ false, false);
+ ctx->addBelInput(dff, id_CLK, w.clk.at(z));
+ ctx->addBelInput(dff, id_D, w.d.at(z));
+ ctx->addBelOutput(dff, id_Q, w.q.at(z));
+ }
+ }
+ // Create bels according to tile type
+ void init_bels()
+ {
+ log_info("Creating bels...\n");
+ for (int y = 0; y < Y; y++) {
+ for (int x = 0; x < X; x++) {
+ if (is_io(x, y)) {
+ if (x == y)
+ continue; // don't put IO in corners
+ add_io_bels(x, y);
+ } else {
+ add_slice_bels(x, y);
+ }
+ }
+ }
+ }
+
+ // Create PIPs inside a tile; following an example synthetic routing pattern
+ void add_tile_pips(int x, int y)
+ {
+ auto &w = wires_by_tile.at(y).at(x);
+ Loc loc(x, y, 0);
+ auto create_input_pips = [&](WireId dst, int offset, int skip) {
+ for (int i = (offset % skip); i < Wl; i += skip)
+ add_pip(loc, w.l.at(i), dst, 0.05);
+ };
+ for (int z = 0; z < N; z++) {
+ create_input_pips(w.clk.at(z), 0, Si);
+ for (int k = 0; k < K; k++)
+ create_input_pips(w.i.at(z * K + k), k, Si);
+ }
+ auto create_output_pips = [&](WireId dst, int offset, int skip) {
+ for (int z = (offset % skip); z < N; z += skip) {
+ add_pip(loc, w.f.at(z), dst, 0.05);
+ add_pip(loc, w.q.at(z), dst, 0.05);
+ }
+ };
+ auto create_neighbour_pips = [&](WireId dst, int nx, int ny, int offset, int skip) {
+ if (nx < 0 || nx >= X)
+ return;
+ if (ny < 0 || ny >= Y)
+ return;
+ auto &nw = wires_by_tile.at(ny).at(nx);
+ for (int i = (offset % skip); i < Wl; i += skip)
+ add_pip(loc, dst, nw.l.at(i), 0.1);
+ };
+ for (int i = 0; i < Wl; i++) {
+ WireId dst = w.l.at(i);
+ create_output_pips(dst, i % Sq, Sq);
+ create_neighbour_pips(dst, x - 1, y - 1, (i + 1) % Sl, Sl);
+ create_neighbour_pips(dst, x - 1, y, (i + 2) % Sl, Sl);
+ create_neighbour_pips(dst, x - 1, y + 1, (i + 3) % Sl, Sl);
+ create_neighbour_pips(dst, x, y - 1, (i + 4) % Sl, Sl);
+ create_neighbour_pips(dst, x, y + 1, (i + 5) % Sl, Sl);
+ create_neighbour_pips(dst, x + 1, y - 1, (i + 6) % Sl, Sl);
+ create_neighbour_pips(dst, x + 1, y, (i + 7) % Sl, Sl);
+ create_neighbour_pips(dst, x + 1, y + 1, (i + 8) % Sl, Sl);
+ }
+ }
+ void init_pips()
+ {
+ log_info("Creating pips...\n");
+ for (int y = 0; y < Y; y++)
+ for (int x = 0; x < X; x++)
+ add_tile_pips(x, y);
+ }
+ // Validity checking
+ struct ExampleCellInfo
+ {
+ const NetInfo *lut_f = nullptr, *ff_d = nullptr;
+ bool lut_i3_used = false;
+ };
+ std::vector<ExampleCellInfo> fast_cell_info;
+ void assign_cell_info()
+ {
+ fast_cell_info.resize(ctx->cells.size());
+ for (auto &cell : ctx->cells) {
+ CellInfo *ci = cell.second.get();
+ auto &fc = fast_cell_info.at(ci->flat_index);
+ if (ci->type == id_LUT4) {
+ fc.lut_f = get_net_or_empty(ci, id_F);
+ fc.lut_i3_used = (get_net_or_empty(ci, ctx->id(stringf("I[%d]", K - 1))) != nullptr);
+ } else if (ci->type == id_DFF) {
+ fc.ff_d = get_net_or_empty(ci, id_D);
+ }
+ }
+ }
+ bool slice_valid(int x, int y, int z) const
+ {
+ const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
+ const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
+ if (!lut || !ff)
+ return true; // always valid if only LUT or FF used
+ const auto &lut_data = fast_cell_info.at(lut->flat_index);
+ const auto &ff_data = fast_cell_info.at(ff->flat_index);
+ // In our example arch; the FF D can either be driven from LUT F or LUT I3
+ // so either; FF D must equal LUT F or LUT I3 must be unused
+ if (ff_data.ff_d == lut_data.lut_f)
+ return true;
+ if (lut_data.lut_i3_used)
+ return false;
+ return true;
+ }
+ // Bel bucket functions
+ IdString getBelBucketForCellType(IdString cell_type) const override
+ {
+ if (cell_type.in(id_INBUF, id_OUTBUF))
+ return id_IOB;
+ return cell_type;
+ }
+ bool isValidBelForCellType(IdString cell_type, BelId bel) const override
+ {
+ IdString bel_type = ctx->getBelType(bel);
+ if (bel_type == id_IOB)
+ return cell_type.in(id_INBUF, id_OUTBUF);
+ else
+ return (bel_type == cell_type);
+ }
+};
+
+struct ExampleArch : ViaductArch
+{
+ ExampleArch() : ViaductArch("example"){};
+ std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args)
+ {
+ return std::make_unique<ExampleImpl>();
+ }
+} exampleArch;
+} // namespace
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct/example/example_map.v b/generic/viaduct/example/example_map.v
new file mode 100644
index 00000000..f701f0ed
--- /dev/null
+++ b/generic/viaduct/example/example_map.v
@@ -0,0 +1,12 @@
+module \$lut (A, Y);
+ parameter WIDTH = 0;
+ parameter LUT = 0;
+ input [WIDTH-1:0] A;
+ output Y;
+
+ localparam rep = 1<<(4-WIDTH);
+
+ LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.I(A), .F(Y));
+endmodule
+
+module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
diff --git a/generic/viaduct/example/example_prims.v b/generic/viaduct/example/example_prims.v
new file mode 100644
index 00000000..d2813129
--- /dev/null
+++ b/generic/viaduct/example/example_prims.v
@@ -0,0 +1,35 @@
+module LUT4 #(
+ parameter [15:0] INIT = 0
+) (
+ input [3:0] I,
+ output F
+);
+ wire [7:0] s3 = I[3] ? INIT[15:8] : INIT[7:0];
+ wire [3:0] s2 = I[2] ? s3[ 7:4] : s3[3:0];
+ wire [1:0] s1 = I[1] ? s2[ 3:2] : s2[1:0];
+ assign F = I[0] ? s1[1] : s1[0];
+endmodule
+
+module DFF (
+ input CLK, D,
+ output reg Q
+);
+ initial Q = 1'b0;
+ always @(posedge CLK)
+ Q <= D;
+endmodule
+
+module INBUF (
+ input PAD,
+ output O,
+);
+ assign O = PAD;
+endmodule
+
+module OUTBUF (
+ output PAD,
+ input I,
+);
+ assign PAD = I;
+endmodule
+
diff --git a/generic/viaduct/example/synth_viaduct_example.tcl b/generic/viaduct/example/synth_viaduct_example.tcl
new file mode 100644
index 00000000..a9d18f56
--- /dev/null
+++ b/generic/viaduct/example/synth_viaduct_example.tcl
@@ -0,0 +1,24 @@
+# Usage
+# tcl synth_viaduct_example.tcl {out.json}
+
+yosys read_verilog -lib [file dirname [file normalize $argv0]]/example_prims.v
+yosys hierarchy -check
+yosys proc
+yosys flatten
+yosys tribuf -logic
+yosys deminout
+yosys synth -run coarse
+yosys memory_map
+yosys opt -full
+yosys iopadmap -bits -inpad INBUF O:PAD -outpad OUTBUF I:PAD
+yosys techmap -map +/techmap.v
+yosys opt -fast
+yosys dfflegalize -cell \$_DFF_P_ 0
+yosys abc -lut 4 -dress
+yosys clean
+yosys techmap -map [file dirname [file normalize $argv0]]/example_map.v
+yosys clean
+yosys hierarchy -check
+yosys stat
+
+if {$argc > 0} { yosys write_json [lindex $argv 0] }
diff --git a/generic/viaduct/example/viaduct_example.sh b/generic/viaduct/example/viaduct_example.sh
new file mode 100755
index 00000000..0842df20
--- /dev/null
+++ b/generic/viaduct/example/viaduct_example.sh
@@ -0,0 +1,6 @@
+#!/usr/bin/env bash
+set -ex
+# Run synthesis
+yosys -p "tcl synth_viaduct_example.tcl blinky.json" ../../examples/blinky.v
+# Run PnR
+${NEXTPNR:-../../../build/nextpnr-generic} --uarch example --json blinky.json
diff --git a/generic/viaduct_api.cc b/generic/viaduct_api.cc
new file mode 100644
index 00000000..8a7b6313
--- /dev/null
+++ b/generic/viaduct_api.cc
@@ -0,0 +1,118 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2021 gatecat <gatecat@ds0.me>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "viaduct_api.h"
+#include "nextpnr.h"
+
+// Default implementations for Viaduct API hooks
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void ViaductAPI::init(Context *ctx) { this->ctx = ctx; }
+
+std::vector<IdString> ViaductAPI::getCellTypes() const
+{
+ pool<IdString> cell_types;
+ for (auto bel : ctx->bels) {
+ cell_types.insert(bel.type);
+ }
+
+ return std::vector<IdString>{cell_types.begin(), cell_types.end()};
+}
+BelBucketId ViaductAPI::getBelBucketForBel(BelId bel) const { return ctx->getBelType(bel); }
+BelBucketId ViaductAPI::getBelBucketForCellType(IdString cell_type) const { return cell_type; }
+bool ViaductAPI::isValidBelForCellType(IdString cell_type, BelId bel) const
+{
+ return ctx->getBelType(bel) == cell_type;
+}
+
+delay_t ViaductAPI::estimateDelay(WireId src, WireId dst) const
+{
+ const WireInfo &s = ctx->wire_info(src);
+ const WireInfo &d = ctx->wire_info(dst);
+ int dx = abs(s.x - d.x);
+ int dy = abs(s.y - d.y);
+ return (dx + dy) * ctx->args.delayScale + ctx->args.delayOffset;
+}
+delay_t ViaductAPI::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const
+{
+ NPNR_UNUSED(src_pin);
+ NPNR_UNUSED(dst_pin);
+ auto driver_loc = ctx->getBelLocation(src_bel);
+ auto sink_loc = ctx->getBelLocation(dst_bel);
+
+ int dx = abs(sink_loc.x - driver_loc.x);
+ int dy = abs(sink_loc.y - driver_loc.y);
+ return (dx + dy) * ctx->args.delayScale + ctx->args.delayOffset;
+}
+ArcBounds ViaductAPI::getRouteBoundingBox(WireId src, WireId dst) const
+{
+ ArcBounds bb;
+ int src_x = ctx->wire_info(src).x;
+ int src_y = ctx->wire_info(src).y;
+ int dst_x = ctx->wire_info(dst).x;
+ int dst_y = ctx->wire_info(dst).y;
+
+ bb.x0 = src_x;
+ bb.y0 = src_y;
+ bb.x1 = src_x;
+ bb.y1 = src_y;
+
+ auto extend = [&](int x, int y) {
+ bb.x0 = std::min(bb.x0, x);
+ bb.x1 = std::max(bb.x1, x);
+ bb.y0 = std::min(bb.y0, y);
+ bb.y1 = std::max(bb.y1, y);
+ };
+ extend(dst_x, dst_y);
+ return bb;
+}
+
+ViaductArch *ViaductArch::list_head;
+ViaductArch::ViaductArch(const std::string &name) : name(name)
+{
+ list_next = ViaductArch::list_head;
+ ViaductArch::list_head = this;
+}
+std::string ViaductArch::list()
+{
+ std::string result;
+ ViaductArch *cursor = ViaductArch::list_head;
+ while (cursor) {
+ if (!result.empty())
+ result += ", ";
+ result += cursor->name;
+ cursor = cursor->list_next;
+ }
+ return result;
+}
+std::unique_ptr<ViaductAPI> ViaductArch::create(const std::string &name, const dict<std::string, std::string> &args)
+{
+ ViaductArch *cursor = ViaductArch::list_head;
+ while (cursor) {
+ if (cursor->name != name) {
+ cursor = cursor->list_next;
+ continue;
+ }
+ return cursor->create(args);
+ }
+ return {};
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct_api.h b/generic/viaduct_api.h
new file mode 100644
index 00000000..bc9b4311
--- /dev/null
+++ b/generic/viaduct_api.h
@@ -0,0 +1,114 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2021 gatecat <gatecat@ds0.me>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef VIADUCT_API_H
+#define VIADUCT_API_H
+
+#include "nextpnr_namespaces.h"
+#include "nextpnr_types.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+/*
+Viaduct -- a series of small arches
+
+Viaduct is a framework that provides an 'inbetween' step between nextpnr-generic
+using Python bindings and a full-custom arch.
+
+It allows an arch to programmatically build a set of bels (placement locations)
+and a routing graph in-memory at startup; and then hook into nextpnr's flow
+and validity checking rules at runtime with custom C++ code.
+
+To create a Viaduct 'uarch', the following are required:
+ - an implementation of ViaductAPI. At a minimum; you will need to use ctx->addBel, ctx->addWire and ctx->addPip to
+create the graph of placement and routing resources in-memory. Also implement any placement validity checking required -
+like rules for how LUTs and FFs can be placed together in a SLICE.
+ - an instance of a struct deriving from ViaductArch - this is how the uarch is discovered. Override create(args) to
+create an instance of your ViaductAPI implementation.
+ - these should be within C++ files in a new subfolder of 'viaduct'. Add the name of this subfolder to the list of
+VIADUCT_UARCHES in family.cmake if building in-tree.
+
+For an example of how these pieces fit together; see 'viaduct/example' which implements a small synthetic architecture
+using this framework.
+
+*/
+
+struct Context;
+
+struct ViaductAPI
+{
+ virtual void init(Context *ctx);
+ Context *ctx;
+
+ // --- Bel functions ---
+ // Called when a bel is placed/unplaced (with cell=nullptr for a unbind)
+ virtual void notifyBelChange(BelId bel, CellInfo *cell) {}
+ // This only needs to return false if a bel is disabled for a microarch-specific reason and not just because it's
+ // bound (which the base generic will deal with)
+ virtual bool checkBelAvail(BelId bel) const { return true; }
+ // Mirror the ArchAPI functions - see archapi.md
+ virtual std::vector<IdString> getCellTypes() const;
+ virtual BelBucketId getBelBucketForBel(BelId bel) const;
+ virtual BelBucketId getBelBucketForCellType(IdString cell_type) const;
+ virtual bool isValidBelForCellType(IdString cell_type, BelId bel) const;
+ virtual bool isBelLocationValid(BelId bel) const { return true; }
+
+ // --- Wire and pip functions ---
+ // Called when a wire/pip is placed/unplaced (with net=nullptr for a unbind)
+ virtual void notifyWireChange(WireId wire, NetInfo *net) {}
+ virtual void notifyPipChange(PipId pip, NetInfo *net) {}
+ // These only need to return false if a wire/pip is disabled for a microarch-specific reason and not just because
+ // it's bound (which the base arch will deal with)
+ virtual bool checkWireAvail(WireId wire) const { return true; }
+ virtual bool checkPipAvail(PipId pip) const { return true; }
+ virtual bool checkPipAvailForNet(PipId pip, NetInfo *net) const { return checkPipAvail(pip); };
+
+ // --- Route lookahead ---
+ virtual delay_t estimateDelay(WireId src, WireId dst) const;
+ virtual delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const;
+ virtual ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
+
+ // --- Flow hooks ---
+ virtual void pack(){}; // replaces the pack function
+ // Called before and after main placement and routing
+ virtual void prePlace(){};
+ virtual void postPlace(){};
+ virtual void preRoute(){};
+ virtual void postRoute(){};
+
+ virtual ~ViaductAPI(){};
+};
+
+struct ViaductArch
+{
+ static ViaductArch *list_head;
+ ViaductArch *list_next = nullptr;
+
+ std::string name;
+ ViaductArch(const std::string &name);
+ ~ViaductArch(){};
+ virtual std::unique_ptr<ViaductAPI> create(const dict<std::string, std::string> &args) = 0;
+
+ static std::string list();
+ static std::unique_ptr<ViaductAPI> create(const std::string &name, const dict<std::string, std::string> &args);
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/generic/viaduct_constids.h b/generic/viaduct_constids.h
new file mode 100644
index 00000000..82180953
--- /dev/null
+++ b/generic/viaduct_constids.h
@@ -0,0 +1,74 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2021 gatecat <gatecat@ds0.me>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef VIADUCT_CONSTIDS_H
+#define VIADUCT_CONSTIDS_H
+
+/*
+This enables use of 'constids' similar to a 'true' nextpnr arch in a viaduct uarch.
+To use:
+ - create a 'constids.inc' file in your uarch folder containing one ID per line; inside X( )
+ - set the VIADUCT_CONSTIDS macro to the path to this file relative to the generic arch base
+ - in your main file; also define GEN_INIT_CONSTIDS to create init_uarch_constids(Context*) which you should call in
+init
+ - include this file
+*/
+
+#include "nextpnr_namespaces.h"
+
+#ifdef VIADUCT_MAIN
+#include "idstring.h"
+#endif
+
+NEXTPNR_NAMESPACE_BEGIN
+
+namespace {
+#ifndef Q_MOC_RUN
+enum ConstIds
+{
+ ID_NONE
+#define X(t) , ID_##t
+#include VIADUCT_CONSTIDS
+#undef X
+ ,
+};
+
+#define X(t) static constexpr auto id_##t = IdString(ID_##t);
+#include VIADUCT_CONSTIDS
+#undef X
+#endif
+
+#ifdef GEN_INIT_CONSTIDS
+
+void init_uarch_constids(Context *ctx)
+{
+#define X(t) IdString::initialize_add(ctx, #t, ID_##t);
+
+#include VIADUCT_CONSTIDS
+
+#undef X
+}
+
+#endif
+
+} // namespace
+
+NEXTPNR_NAMESPACE_END
+
+#endif
diff --git a/generic/viaduct_helpers.cc b/generic/viaduct_helpers.cc
new file mode 100644
index 00000000..36bdd6be
--- /dev/null
+++ b/generic/viaduct_helpers.cc
@@ -0,0 +1,163 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2021 gatecat <gatecat@ds0.me>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "viaduct_helpers.h"
+#include "design_utils.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+void ViaductHelpers::resize_ids(int x, int y)
+{
+ NPNR_ASSERT(x >= 0 && y >= 0 && x <= 20000 && y <= 20000);
+ while (int(x_ids.size()) <= x) {
+ IdString next = ctx->id(stringf("X%d", int(x_ids.size())));
+ x_ids.push_back(next);
+ }
+ while (int(y_ids.size()) <= y) {
+ IdString next = ctx->id(stringf("Y%d", int(y_ids.size())));
+ y_ids.push_back(next);
+ }
+}
+
+IdStringList ViaductHelpers::xy_id(int x, int y, IdString base)
+{
+ resize_ids(x, y);
+ std::array<IdString, 3> result{x_ids.at(x), y_ids.at(y), base};
+ return IdStringList(result);
+}
+
+IdStringList ViaductHelpers::xy_id(int x, int y, IdStringList base)
+{
+ resize_ids(x, y);
+ std::array<IdString, 2> prefix{x_ids.at(x), y_ids.at(y)};
+ return IdStringList::concat(IdStringList(prefix), base);
+}
+
+void ViaductHelpers::remove_nextpnr_iobs(const pool<CellTypePort> &top_ports)
+{
+ std::vector<IdString> to_remove;
+ for (auto &cell : ctx->cells) {
+ auto &ci = *cell.second;
+ if (!ci.type.in(ctx->id("$nextpnr_ibuf"), ctx->id("$nextpnr_obuf"), ctx->id("$nextpnr_iobuf")))
+ continue;
+ NetInfo *i = get_net_or_empty(&ci, ctx->id("I"));
+ if (i && i->driver.cell) {
+ if (!top_ports.count(CellTypePort(i->driver)))
+ log_error("Top-level port '%s' driven by illegal port %s.%s\n", ctx->nameOf(&ci),
+ ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
+ }
+ NetInfo *o = get_net_or_empty(&ci, ctx->id("O"));
+ if (o) {
+ for (auto &usr : o->users) {
+ if (!top_ports.count(CellTypePort(usr)))
+ log_error("Top-level port '%s' driving illegal port %s.%s\n", ctx->nameOf(&ci),
+ ctx->nameOf(usr.cell), ctx->nameOf(usr.port));
+ }
+ }
+ disconnect_port(ctx, &ci, ctx->id("I"));
+ disconnect_port(ctx, &ci, ctx->id("O"));
+ to_remove.push_back(ci.name);
+ }
+ for (IdString cell_name : to_remove)
+ ctx->cells.erase(cell_name);
+}
+
+int ViaductHelpers::constrain_cell_pairs(const pool<CellTypePort> &src_ports, const pool<CellTypePort> &sink_ports,
+ int delta_z)
+{
+ int constrained = 0;
+ for (auto &cell : ctx->cells) {
+ auto &ci = *cell.second;
+ if (ci.cluster != ClusterId())
+ continue; // don't constrain already-constrained cells
+ bool done = false;
+ for (auto &port : ci.ports) {
+ // look for starting source ports
+ if (port.second.type != PORT_OUT || !port.second.net)
+ continue;
+ if (!src_ports.count(CellTypePort(ci.type, port.first)))
+ continue;
+ for (auto &usr : port.second.net->users) {
+ if (!sink_ports.count(CellTypePort(usr)))
+ continue;
+ if (usr.cell->cluster != ClusterId())
+ continue;
+ // Add the constraint
+ ci.cluster = ci.name;
+ ci.constr_abs_z = false;
+ ci.constr_children.push_back(usr.cell);
+ usr.cell->cluster = ci.name;
+ usr.cell->constr_x = 0;
+ usr.cell->constr_y = 0;
+ usr.cell->constr_z = delta_z;
+ usr.cell->constr_abs_z = false;
+ ++constrained;
+ done = true;
+ break;
+ }
+ if (done)
+ break;
+ }
+ }
+ return constrained;
+}
+
+void ViaductHelpers::replace_constants(CellTypePort vcc_driver, CellTypePort gnd_driver,
+ const dict<IdString, Property> &vcc_params,
+ const dict<IdString, Property> &gnd_params)
+{
+ CellInfo *vcc_drv = ctx->createCell(ctx->id("$PACKER_VCC_DRV"), vcc_driver.cell_type);
+ vcc_drv->addOutput(vcc_driver.port);
+ for (auto &p : vcc_params)
+ vcc_drv->params[p.first] = p.second;
+
+ CellInfo *gnd_drv = ctx->createCell(ctx->id("$PACKER_GND_DRV"), gnd_driver.cell_type);
+ gnd_drv->addOutput(gnd_driver.port);
+ for (auto &p : gnd_params)
+ gnd_drv->params[p.first] = p.second;
+
+ NetInfo *vcc_net = ctx->createNet(ctx->id("$PACKER_VCC"));
+ NetInfo *gnd_net = ctx->createNet(ctx->id("$PACKER_GND"));
+
+ std::vector<IdString> trim_cells;
+ std::vector<IdString> trim_nets;
+ for (auto &net : ctx->nets) {
+ auto &ni = *net.second;
+ if (!ni.driver.cell)
+ continue;
+ if (ni.driver.cell->type != ctx->id("GND") && ni.driver.cell->type != ctx->id("VCC"))
+ continue;
+ NetInfo *replace = (ni.driver.cell->type == ctx->id("VCC")) ? vcc_net : gnd_net;
+ for (auto &usr : ni.users) {
+ usr.cell->ports.at(usr.port).net = replace;
+ replace->users.push_back(usr);
+ }
+ trim_cells.push_back(ni.driver.cell->name);
+ trim_nets.push_back(ni.name);
+ }
+ for (IdString cell_name : trim_cells)
+ ctx->cells.erase(cell_name);
+ for (IdString net_name : trim_nets)
+ ctx->nets.erase(net_name);
+}
+
+NEXTPNR_NAMESPACE_END
diff --git a/generic/viaduct_helpers.h b/generic/viaduct_helpers.h
new file mode 100644
index 00000000..8cba8411
--- /dev/null
+++ b/generic/viaduct_helpers.h
@@ -0,0 +1,82 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2021 gatecat <gatecat@ds0.me>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef VIADUCT_HELPERS_H
+#define VIADUCT_HELPERS_H
+
+#include "nextpnr_namespaces.h"
+#include "nextpnr_types.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+/*
+Viaduct -- a series of small arches
+
+See viaduct_api.h for more background.
+
+viaduct_helpers provides some features for building up arches using the viaduct API
+*/
+
+// Used to configure various generic pack functions
+struct CellTypePort
+{
+ CellTypePort() : cell_type(), port(){};
+ CellTypePort(IdString cell_type, IdString port) : cell_type(cell_type), port(port){};
+ explicit CellTypePort(const PortRef &net_port)
+ : cell_type(net_port.cell ? net_port.cell->type : IdString()), port(net_port.port){};
+ inline bool operator==(const CellTypePort &other) const
+ {
+ return cell_type == other.cell_type && port == other.port;
+ }
+ inline bool operator!=(const CellTypePort &other) const
+ {
+ return cell_type != other.cell_type || port != other.port;
+ }
+ inline unsigned hash() const { return mkhash(cell_type.hash(), port.hash()); }
+ IdString cell_type, port;
+};
+
+struct ViaductHelpers
+{
+ ViaductHelpers(){};
+ Context *ctx;
+ void init(Context *ctx) { this->ctx = ctx; }
+ // IdStringList components for x and y locations
+ std::vector<IdString> x_ids, y_ids;
+ void resize_ids(int x, int y);
+ // Get an IdStringList for a hierarchical ID
+ // Because this uses an IdStringList with seperate X and Y components; this will be much more efficient than
+ // creating unique strings for each object in each X and Y position
+ IdStringList xy_id(int x, int y, IdString base);
+ IdStringList xy_id(int x, int y, IdStringList base);
+ // Common packing functions
+ // Remove nextpnr-inserted IO buffers; where IO buffer insertion is done in synthesis
+ // expects a set of top-level port types
+ void remove_nextpnr_iobs(const pool<CellTypePort> &top_ports);
+ // Constrain cells with certain port connection patterns together with a fixed z-offset
+ int constrain_cell_pairs(const pool<CellTypePort> &src_ports, const pool<CellTypePort> &sink_ports, int delta_z);
+ // Replace constants with given driving cells
+ void replace_constants(CellTypePort vcc_driver, CellTypePort gnd_driver,
+ const dict<IdString, Property> &vcc_params = {},
+ const dict<IdString, Property> &gnd_params = {});
+};
+
+NEXTPNR_NAMESPACE_END
+
+#endif
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