diff options
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/arch.cc | 4 | ||||
| -rw-r--r-- | fpga_interchange/arch.h | 2 | ||||
| -rw-r--r-- | fpga_interchange/examples/devices/xc7a35t/test_data.yaml | 4 |
3 files changed, 7 insertions, 3 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index 96169cf2..a3a8a166 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -1617,7 +1617,7 @@ void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength) refreshUiWire(wire); } -bool Arch::check_pip_avail_for_net(PipId pip, NetInfo *net) const +bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const { NPNR_ASSERT(pip != PipId()); auto pip_iter = pip_to_net.find(pip); @@ -1755,7 +1755,7 @@ bool Arch::check_pip_avail_for_net(PipId pip, NetInfo *net) const return true; } -bool Arch::checkPipAvail(PipId pip) const { return check_pip_avail_for_net(pip, nullptr); } +bool Arch::checkPipAvail(PipId pip) const { return checkPipAvailForNet(pip, nullptr); } // Instance constraint templates. template void Arch::ArchConstraints::bindBel(Arch::ArchConstraints::TagState *, const Arch::ConstraintRange); diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 005bbb41..217e3508 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -537,7 +537,7 @@ struct Arch : ArchAPI<ArchRanges> void unbindPip(PipId pip) final; bool checkPipAvail(PipId pip) const final; - bool check_pip_avail_for_net(PipId pip, NetInfo *) const; + bool checkPipAvailForNet(PipId pip, NetInfo *net) const final; NetInfo *getBoundPipNet(PipId pip) const final { diff --git a/fpga_interchange/examples/devices/xc7a35t/test_data.yaml b/fpga_interchange/examples/devices/xc7a35t/test_data.yaml index 268d180a..88c6feda 100644 --- a/fpga_interchange/examples/devices/xc7a35t/test_data.yaml +++ b/fpga_interchange/examples/devices/xc7a35t/test_data.yaml @@ -34,3 +34,7 @@ bel_pin_test: - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC pin: P wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE + - bel: SLICE_X1Y19.SLICEL/SRUSEDGND + pin: "0" + wire: SLICE_X1Y19.SLICEL/SRUSEDGND_HARD0 + type: PORT_OUT |