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-rw-r--r--fpga_interchange/examples/tests/ram/run.tcl17
1 files changed, 17 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/ram/run.tcl b/fpga_interchange/examples/tests/ram/run.tcl
new file mode 100644
index 00000000..79321139
--- /dev/null
+++ b/fpga_interchange/examples/tests/ram/run.tcl
@@ -0,0 +1,17 @@
+yosys -import
+
+foreach src $::env(SOURCES) {
+ read_verilog $src
+}
+
+synth_xilinx -flatten -nolutram -nowidelut -nosrl -nocarry -nodsp
+techmap -map $::env(TECHMAP)
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)