diff options
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/arch.cc | 184 | ||||
| -rw-r--r-- | ecp5/arch.h | 263 | ||||
| -rw-r--r-- | ecp5/arch_pybindings.h | 18 | ||||
| -rw-r--r-- | ecp5/bitstream.cc | 5 |
4 files changed, 182 insertions, 288 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 1938c297..51f4db84 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -151,7 +151,7 @@ IdString Arch::archArgsToId(ArchArgs args) const // ----------------------------------------------------------------------- -BelId ArchReadMethods::getBelByName(IdString name) const +BelId Arch::getBelByName(IdString name) const { BelId ret; auto it = bel_by_name.find(name); @@ -160,9 +160,9 @@ BelId ArchReadMethods::getBelByName(IdString name) const Location loc; std::string basename; - std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(parent_)); + std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this)); ret.location = loc; - const LocationTypePOD *loci = parent_->locInfo(ret); + const LocationTypePOD *loci = locInfo(ret); for (int i = 0; i < loci->num_bels; i++) { if (std::strcmp(loci->bel_data[i].name.get(), basename.c_str()) == 0) { ret.index = i; @@ -185,14 +185,14 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const return br; } -WireId ArchReadMethods::getWireBelPin(BelId bel, PortPin pin) const +WireId Arch::getWireBelPin(BelId bel, PortPin pin) const { WireId ret; NPNR_ASSERT(bel != BelId()); - int num_bel_wires = parent_->locInfo(bel)->bel_data[bel.index].num_bel_wires; - const BelWirePOD *bel_wires = parent_->locInfo(bel)->bel_data[bel.index].bel_wires.get(); + int num_bel_wires = locInfo(bel)->bel_data[bel.index].num_bel_wires; + const BelWirePOD *bel_wires = locInfo(bel)->bel_data[bel.index].bel_wires.get(); for (int i = 0; i < num_bel_wires; i++) if (bel_wires[i].port == pin) { ret.location = bel.location + bel_wires[i].rel_wire_loc; @@ -205,7 +205,7 @@ WireId ArchReadMethods::getWireBelPin(BelId bel, PortPin pin) const // ----------------------------------------------------------------------- -WireId ArchReadMethods::getWireByName(IdString name) const +WireId Arch::getWireByName(IdString name) const { WireId ret; auto it = wire_by_name.find(name); @@ -214,9 +214,9 @@ WireId ArchReadMethods::getWireByName(IdString name) const Location loc; std::string basename; - std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(parent_)); + std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this)); ret.location = loc; - const LocationTypePOD *loci = parent_->locInfo(ret); + const LocationTypePOD *loci = locInfo(ret); for (int i = 0; i < loci->num_wires; i++) { if (std::strcmp(loci->wire_data[i].name.get(), basename.c_str()) == 0) { ret.index = i; @@ -233,7 +233,7 @@ WireId ArchReadMethods::getWireByName(IdString name) const // ----------------------------------------------------------------------- -PipId ArchReadMethods::getPipByName(IdString name) const +PipId Arch::getPipByName(IdString name) const { auto it = pip_by_name.find(name); if (it != pip_by_name.end()) @@ -242,13 +242,13 @@ PipId ArchReadMethods::getPipByName(IdString name) const PipId ret; Location loc; std::string basename; - std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(parent_)); - const LocationTypePOD *loci = parent_->locInfo(ret); + std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this)); + const LocationTypePOD *loci = locInfo(ret); for (int i = 0; i < loci->num_pips; i++) { PipId curr; curr.location = loc; curr.index = i; - pip_by_name[parent_->getPipName(curr)] = curr; + pip_by_name[getPipName(curr)] = curr; } return pip_by_name[name]; } @@ -296,7 +296,7 @@ bool Arch::route() { return router1(getCtx()); } // ----------------------------------------------------------------------- -std::vector<GraphicElement> ArchReadMethods::getDecalGraphics(DecalId decalId) const +std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decalId) const { std::vector<GraphicElement> ret; // FIXME @@ -315,9 +315,9 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; }; // ----------------------------------------------------------------------- -bool ArchReadMethods::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; } +bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; } -bool ArchReadMethods::isBelLocationValid(BelId bel) const { return true; } +bool Arch::isBelLocationValid(BelId bel) const { return true; } // ----------------------------------------------------------------------- @@ -330,156 +330,4 @@ IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; } -bool ArchReadMethods::checkWireAvail(WireId wire) const -{ - NPNR_ASSERT(wire != WireId()); - return wire_to_net.find(wire) == wire_to_net.end() || wire_to_net.at(wire) == IdString(); -} - -bool ArchReadMethods::checkPipAvail(PipId pip) const -{ - NPNR_ASSERT(pip != PipId()); - return pip_to_net.find(pip) == pip_to_net.end() || pip_to_net.at(pip) == IdString(); -} - -bool ArchReadMethods::checkBelAvail(BelId bel) const -{ - NPNR_ASSERT(bel != BelId()); - return bel_to_cell.find(bel) == bel_to_cell.end() || bel_to_cell.at(bel) == IdString(); -} - -IdString ArchReadMethods::getConflictingBelCell(BelId bel) const -{ - NPNR_ASSERT(bel != BelId()); - if (bel_to_cell.find(bel) == bel_to_cell.end()) - return IdString(); - else - return bel_to_cell.at(bel); -} - -IdString ArchReadMethods::getConflictingWireNet(WireId wire) const -{ - NPNR_ASSERT(wire != WireId()); - if (wire_to_net.find(wire) == wire_to_net.end()) - return IdString(); - else - return wire_to_net.at(wire); -} - -IdString ArchReadMethods::getConflictingPipNet(PipId pip) const -{ - NPNR_ASSERT(pip != PipId()); - if (pip_to_net.find(pip) == pip_to_net.end()) - return IdString(); - else - return pip_to_net.at(pip); -} - -IdString ArchReadMethods::getBoundWireNet(WireId wire) const -{ - NPNR_ASSERT(wire != WireId()); - if (wire_to_net.find(wire) == wire_to_net.end()) - return IdString(); - else - return wire_to_net.at(wire); -} - -IdString ArchReadMethods::getBoundPipNet(PipId pip) const -{ - NPNR_ASSERT(pip != PipId()); - if (pip_to_net.find(pip) == pip_to_net.end()) - return IdString(); - else - return pip_to_net.at(pip); -} - -IdString ArchReadMethods::getBoundBelCell(BelId bel) const -{ - NPNR_ASSERT(bel != BelId()); - if (bel_to_cell.find(bel) == bel_to_cell.end()) - return IdString(); - else - return bel_to_cell.at(bel); -} - -void ArchMutateMethods::unbindWire(WireId wire) -{ - NPNR_ASSERT(wire != WireId()); - NPNR_ASSERT(wire_to_net[wire] != IdString()); - - auto &net_wires = parent_->nets[wire_to_net[wire]]->wires; - auto it = net_wires.find(wire); - NPNR_ASSERT(it != net_wires.end()); - - auto pip = it->second.pip; - if (pip != PipId()) { - pip_to_net[pip] = IdString(); - } - - net_wires.erase(it); - wire_to_net[wire] = IdString(); -} - -void ArchMutateMethods::unbindPip(PipId pip) -{ - NPNR_ASSERT(pip != PipId()); - NPNR_ASSERT(pip_to_net[pip] != IdString()); - - WireId dst; - dst.index = parent_->locInfo(pip)->pip_data[pip.index].dst_idx; - dst.location = pip.location + parent_->locInfo(pip)->pip_data[pip.index].rel_dst_loc; - NPNR_ASSERT(wire_to_net[dst] != IdString()); - wire_to_net[dst] = IdString(); - parent_->nets[pip_to_net[pip]]->wires.erase(dst); - - pip_to_net[pip] = IdString(); -} - -void ArchMutateMethods::unbindBel(BelId bel) -{ - NPNR_ASSERT(bel != BelId()); - NPNR_ASSERT(bel_to_cell[bel] != IdString()); - parent_->cells[bel_to_cell[bel]]->bel = BelId(); - parent_->cells[bel_to_cell[bel]]->belStrength = STRENGTH_NONE; - bel_to_cell[bel] = IdString(); -} - -void ArchMutateMethods::bindWire(WireId wire, IdString net, PlaceStrength strength) -{ - NPNR_ASSERT(wire != WireId()); - NPNR_ASSERT(wire_to_net[wire] == IdString()); - wire_to_net[wire] = net; - parent_->nets[net]->wires[wire].pip = PipId(); - parent_->nets[net]->wires[wire].strength = strength; -} - -void ArchMutateMethods::bindPip(PipId pip, IdString net, PlaceStrength strength) -{ - NPNR_ASSERT(pip != PipId()); - NPNR_ASSERT(pip_to_net[pip] == IdString()); - - pip_to_net[pip] = net; - - WireId dst; - dst.index = parent_->locInfo(pip)->pip_data[pip.index].dst_idx; - dst.location = pip.location + parent_->locInfo(pip)->pip_data[pip.index].rel_dst_loc; - NPNR_ASSERT(wire_to_net[dst] == IdString()); - wire_to_net[dst] = net; - parent_->nets[net]->wires[dst].pip = pip; - parent_->nets[net]->wires[dst].strength = strength; -} - -void ArchMutateMethods::bindBel(BelId bel, IdString cell, PlaceStrength strength) -{ - NPNR_ASSERT(bel != BelId()); - NPNR_ASSERT(bel_to_cell[bel] == IdString()); - bel_to_cell[bel] = cell; - parent_->cells[cell]->bel = bel; - parent_->cells[cell]->belStrength = strength; -} - -CellInfo *ArchMutateMethods::getCell(IdString cell) { return parent_->cells.at(cell).get(); } - - - NEXTPNR_NAMESPACE_END diff --git a/ecp5/arch.h b/ecp5/arch.h index 06cf6488..930c488e 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -339,10 +339,8 @@ struct ArchArgs struct Arch : BaseCtx { - // We let proxy methods access our state. - friend class ArchMutateMethods; - friend class ArchReadMethods; -private: + const ChipInfoPOD *chip_info; + mutable std::unordered_map<IdString, BelId> bel_by_name; mutable std::unordered_map<IdString, WireId> wire_by_name; mutable std::unordered_map<IdString, PipId> pip_by_name; @@ -352,9 +350,6 @@ private: std::unordered_map<PipId, IdString> pip_to_net; std::unordered_map<PipId, IdString> switches_locked; -public: - const ChipInfoPOD *chip_info; - ArchArgs args; Arch(ArchArgs args); @@ -371,6 +366,8 @@ public: // ------------------------------------------------- + BelId getBelByName(IdString name) const; + template <typename Id> const LocationTypePOD *locInfo(Id &id) const { return &(chip_info->locations[chip_info->location_type[id.location.y * chip_info->width + id.location.x]]); @@ -386,6 +383,48 @@ public: uint32_t getBelChecksum(BelId bel) const { return bel.index; } + void bindBel(BelId bel, IdString cell, PlaceStrength strength) + { + NPNR_ASSERT(bel != BelId()); + NPNR_ASSERT(bel_to_cell[bel] == IdString()); + bel_to_cell[bel] = cell; + cells[cell]->bel = bel; + cells[cell]->belStrength = strength; + } + + void unbindBel(BelId bel) + { + NPNR_ASSERT(bel != BelId()); + NPNR_ASSERT(bel_to_cell[bel] != IdString()); + cells[bel_to_cell[bel]]->bel = BelId(); + cells[bel_to_cell[bel]]->belStrength = STRENGTH_NONE; + bel_to_cell[bel] = IdString(); + } + + bool checkBelAvail(BelId bel) const + { + NPNR_ASSERT(bel != BelId()); + return bel_to_cell.find(bel) == bel_to_cell.end() || bel_to_cell.at(bel) == IdString(); + } + + IdString getBoundBelCell(BelId bel) const + { + NPNR_ASSERT(bel != BelId()); + if (bel_to_cell.find(bel) == bel_to_cell.end()) + return IdString(); + else + return bel_to_cell.at(bel); + } + + IdString getConflictingBelCell(BelId bel) const + { + NPNR_ASSERT(bel != BelId()); + if (bel_to_cell.find(bel) == bel_to_cell.end()) + return IdString(); + else + return bel_to_cell.at(bel); + } + BelRange getBels() const { BelRange range; @@ -421,6 +460,8 @@ public: return locInfo(bel)->bel_data[bel.index].type; } + WireId getWireBelPin(BelId bel, PortPin pin) const; + BelPin getBelPinUphill(WireId wire) const { BelPin ret; @@ -448,6 +489,8 @@ public: // ------------------------------------------------- + WireId getWireByName(IdString name) const; + IdString getWireName(WireId wire) const { NPNR_ASSERT(wire != WireId()); @@ -460,6 +503,57 @@ public: uint32_t getWireChecksum(WireId wire) const { return wire.index; } + void bindWire(WireId wire, IdString net, PlaceStrength strength) + { + NPNR_ASSERT(wire != WireId()); + NPNR_ASSERT(wire_to_net[wire] == IdString()); + wire_to_net[wire] = net; + nets[net]->wires[wire].pip = PipId(); + nets[net]->wires[wire].strength = strength; + } + + void unbindWire(WireId wire) + { + NPNR_ASSERT(wire != WireId()); + NPNR_ASSERT(wire_to_net[wire] != IdString()); + + auto &net_wires = nets[wire_to_net[wire]]->wires; + auto it = net_wires.find(wire); + NPNR_ASSERT(it != net_wires.end()); + + auto pip = it->second.pip; + if (pip != PipId()) { + pip_to_net[pip] = IdString(); + } + + net_wires.erase(it); + wire_to_net[wire] = IdString(); + } + + bool checkWireAvail(WireId wire) const + { + NPNR_ASSERT(wire != WireId()); + return wire_to_net.find(wire) == wire_to_net.end() || wire_to_net.at(wire) == IdString(); + } + + IdString getBoundWireNet(WireId wire) const + { + NPNR_ASSERT(wire != WireId()); + if (wire_to_net.find(wire) == wire_to_net.end()) + return IdString(); + else + return wire_to_net.at(wire); + } + + IdString getConflictingWireNet(WireId wire) const + { + NPNR_ASSERT(wire != WireId()); + if (wire_to_net.find(wire) == wire_to_net.end()) + return IdString(); + else + return wire_to_net.at(wire); + } + WireRange getWires() const { WireRange range; @@ -475,10 +569,66 @@ public: // ------------------------------------------------- + PipId getPipByName(IdString name) const; IdString getPipName(PipId pip) const; uint32_t getPipChecksum(PipId pip) const { return pip.index; } + void bindPip(PipId pip, IdString net, PlaceStrength strength) + { + NPNR_ASSERT(pip != PipId()); + NPNR_ASSERT(pip_to_net[pip] == IdString()); + + pip_to_net[pip] = net; + + WireId dst; + dst.index = locInfo(pip)->pip_data[pip.index].dst_idx; + dst.location = pip.location + locInfo(pip)->pip_data[pip.index].rel_dst_loc; + NPNR_ASSERT(wire_to_net[dst] == IdString()); + wire_to_net[dst] = net; + nets[net]->wires[dst].pip = pip; + nets[net]->wires[dst].strength = strength; + } + + void unbindPip(PipId pip) + { + NPNR_ASSERT(pip != PipId()); + NPNR_ASSERT(pip_to_net[pip] != IdString()); + + WireId dst; + dst.index = locInfo(pip)->pip_data[pip.index].dst_idx; + dst.location = pip.location + locInfo(pip)->pip_data[pip.index].rel_dst_loc; + NPNR_ASSERT(wire_to_net[dst] != IdString()); + wire_to_net[dst] = IdString(); + nets[pip_to_net[pip]]->wires.erase(dst); + + pip_to_net[pip] = IdString(); + } + + bool checkPipAvail(PipId pip) const + { + NPNR_ASSERT(pip != PipId()); + return pip_to_net.find(pip) == pip_to_net.end() || pip_to_net.at(pip) == IdString(); + } + + IdString getBoundPipNet(PipId pip) const + { + NPNR_ASSERT(pip != PipId()); + if (pip_to_net.find(pip) == pip_to_net.end()) + return IdString(); + else + return pip_to_net.at(pip); + } + + IdString getConflictingPipNet(PipId pip) const + { + NPNR_ASSERT(pip != PipId()); + if (pip_to_net.find(pip) == pip_to_net.end()) + return IdString(); + else + return pip_to_net.at(pip); + } + AllPipRange getPips() const { AllPipRange range; @@ -561,7 +711,6 @@ public: // ------------------------------------------------- - // TODO(q3k) move this to archproxies? GroupId getGroupByName(IdString name) const { return GroupId(); } IdString getGroupName(GroupId group) const { return IdString(); } std::vector<GroupId> getGroups() const { return std::vector<GroupId>(); } @@ -572,8 +721,6 @@ public: // ------------------------------------------------- - // These are also specific to the chip and not state, so they're available - // on arch directly. void estimatePosition(BelId bel, int &x, int &y, bool &gb) const; delay_t estimateDelay(WireId src, WireId dst) const; delay_t getDelayEpsilon() const { return 20; } @@ -589,7 +736,8 @@ public: // ------------------------------------------------- - // TODO(q3k) move this to archproxies? + std::vector<GraphicElement> getDecalGraphics(DecalId decal) const; + DecalXY getFrameDecal() const; DecalXY getBelDecal(BelId bel) const; DecalXY getWireDecal(WireId wire) const; @@ -607,100 +755,11 @@ public: bool isClockPort(const CellInfo *cell, IdString port) const; // Return true if a port is a net bool isGlobalNet(const NetInfo *net) const; -}; - -class ArchReadMethods : public BaseReadCtx -{ - private: - const Arch *parent_; - const ChipInfoPOD *chip_info; - const std::unordered_map<BelId, IdString> &bel_to_cell; - const std::unordered_map<WireId, IdString> &wire_to_net; - const std::unordered_map<PipId, IdString> &pip_to_net; - const std::unordered_map<PipId, IdString> &switches_locked; - std::unordered_map<IdString, BelId> &bel_by_name; - std::unordered_map<IdString, WireId> &wire_by_name; - std::unordered_map<IdString, PipId> &pip_by_name; - - public: - ~ArchReadMethods() noexcept {} - ArchReadMethods(const Arch *parent) - : BaseReadCtx(parent), parent_(parent), chip_info(parent->chip_info), bel_to_cell(parent->bel_to_cell), - wire_to_net(parent->wire_to_net), pip_to_net(parent->pip_to_net), - switches_locked(parent->switches_locked), bel_by_name(parent->bel_by_name), - wire_by_name(parent->wire_by_name), pip_by_name(parent->pip_by_name) - { - } - ArchReadMethods(ArchReadMethods &&other) noexcept : ArchReadMethods(other.parent_) {} - ArchReadMethods(const ArchReadMethods &other) : ArchReadMethods(other.parent_) {} - - /// Perform placement validity checks, returning false on failure (all implemented in arch_place.cc) - // Whether or not a given cell can be placed at a given Bel - // This is not intended for Bel type checks, but finer-grained constraints - // such as conflicting set/reset signals, etc + // ------------------------------------------------- + // Placement validity checks bool isValidBelForCell(CellInfo *cell, BelId bel) const; - // Return true whether all Bels at a given location are valid bool isBelLocationValid(BelId bel) const; - - bool checkWireAvail(WireId wire) const; - bool checkPipAvail(PipId pip) const; - bool checkBelAvail(BelId bel) const; - - WireId getWireByName(IdString name) const; - WireId getWireBelPin(BelId bel, PortPin pin) const; - PipId getPipByName(IdString name) const; - - IdString getConflictingWireNet(WireId wire) const; - IdString getConflictingPipNet(PipId pip) const; - IdString getConflictingBelCell(BelId bel) const; - - IdString getBoundWireNet(WireId wire) const; - IdString getBoundPipNet(PipId pip) const; - IdString getBoundBelCell(BelId bel) const; - - BelId getBelByName(IdString name) const; - - std::vector<GraphicElement> getDecalGraphics(DecalId decal) const; }; -class ArchMutateMethods : public BaseMutateCtx -{ - friend class MutateContext; - - private: - Arch *parent_; - const ChipInfoPOD *chip_info; - - std::unordered_map<BelId, IdString> &bel_to_cell; - std::unordered_map<WireId, IdString> &wire_to_net; - std::unordered_map<PipId, IdString> &pip_to_net; - std::unordered_map<PipId, IdString> &switches_locked; - std::unordered_map<IdString, BelId> &bel_by_name; - std::unordered_map<IdString, WireId> &wire_by_name; - std::unordered_map<IdString, PipId> &pip_by_name; - - public: - ~ArchMutateMethods() noexcept {} - ArchMutateMethods(Arch *parent) - : BaseMutateCtx(parent), parent_(parent), chip_info(parent->chip_info), bel_to_cell(parent->bel_to_cell), - wire_to_net(parent->wire_to_net), pip_to_net(parent->pip_to_net), - switches_locked(parent->switches_locked), bel_by_name(parent->bel_by_name), - wire_by_name(parent->wire_by_name), pip_by_name(parent->pip_by_name) - { - } - ArchMutateMethods(ArchMutateMethods &&other) noexcept : ArchMutateMethods(other.parent_) {} - ArchMutateMethods(const ArchMutateMethods &other) : ArchMutateMethods(other.parent_) {} - - void unbindWire(WireId wire); - void unbindPip(PipId pip); - void unbindBel(BelId bel); - void bindWire(WireId wire, IdString net, PlaceStrength strength); - void bindPip(PipId pip, IdString net, PlaceStrength strength); - void bindBel(BelId bel, IdString cell, PlaceStrength strength); - // Returned pointer is valid as long as Proxy object exists. - CellInfo *getCell(IdString cell); -}; - - NEXTPNR_NAMESPACE_END diff --git a/ecp5/arch_pybindings.h b/ecp5/arch_pybindings.h index 6256af18..a5044f29 100644 --- a/ecp5/arch_pybindings.h +++ b/ecp5/arch_pybindings.h @@ -30,11 +30,7 @@ namespace PythonConversion { template <> struct string_converter<BelId> { - BelId from_str(Context *ctx, std::string name) - { - auto &&proxy = ctx->rproxy(); - return proxy.getBelByName(ctx->id(name)); - } + BelId from_str(Context *ctx, std::string name) { return ctx->getBelByName(ctx->id(name)); } std::string to_str(Context *ctx, BelId id) { @@ -53,22 +49,14 @@ template <> struct string_converter<BelType> template <> struct string_converter<WireId> { - WireId from_str(Context *ctx, std::string name) - { - auto &&proxy = ctx->rproxy(); - return proxy.getWireByName(ctx->id(name)); - } + WireId from_str(Context *ctx, std::string name) { return ctx->getWireByName(ctx->id(name)); } std::string to_str(Context *ctx, WireId id) { return ctx->getWireName(id).str(ctx); } }; template <> struct string_converter<PipId> { - PipId from_str(Context *ctx, std::string name) - { - auto &&proxy = ctx->rproxy(); - return proxy.getPipByName(ctx->id(name)); - } + PipId from_str(Context *ctx, std::string name) { return ctx->getPipByName(ctx->id(name)); } std::string to_str(Context *ctx, PipId id) { return ctx->getPipName(id).str(ctx); } }; diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index b2376391..e70d6bb2 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -155,7 +155,6 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex { Trellis::Chip empty_chip(ctx->getChipName()); Trellis::ChipConfig cc; - auto &&proxy = ctx->rproxy(); std::set<std::string> cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"}; @@ -173,7 +172,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex // Add all set, configurable pips to the config for (auto pip : ctx->getPips()) { - if (proxy.getBoundPipNet(pip) != IdString()) { + if (ctx->getBoundPipNet(pip) != IdString()) { if (ctx->getPipType(pip) == 0) { // ignore fixed pips std::string tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x, ctx->getPipTiletype(pip)); @@ -228,7 +227,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) { // Tie tristate low if unconnected for outputs or bidir std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back()); - WireId jpt_wire = proxy.getWireByName(ctx->id(jpt)); + WireId jpt_wire = ctx->getWireByName(ctx->id(jpt)); PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin(); WireId cib_wire = ctx->getPipSrcWire(jpt_pip); std::string cib_tile = |