diff options
Diffstat (limited to 'ecp5/constids.inc')
| -rw-r--r-- | ecp5/constids.inc | 307 |
1 files changed, 307 insertions, 0 deletions
diff --git a/ecp5/constids.inc b/ecp5/constids.inc index bdcbc1ea..11ecc240 100644 --- a/ecp5/constids.inc +++ b/ecp5/constids.inc @@ -810,3 +810,310 @@ X(LOCK) X(INTLOCK) X(REFCLK) X(CLKINTFB) + + +X(EXTREFB) +X(REFCLKP) +X(REFCLKN) +X(REFCLKO) + +X(DCUA) +X(CH0_HDINP) +X(CH1_HDINP) +X(CH0_HDINN) +X(CH1_HDINN) +X(D_TXBIT_CLKP_FROM_ND) +X(D_TXBIT_CLKN_FROM_ND) +X(D_SYNC_ND) +X(D_TXPLL_LOL_FROM_ND) +X(CH0_RX_REFCLK) +X(CH1_RX_REFCLK) +X(CH0_FF_RXI_CLK) +X(CH1_FF_RXI_CLK) +X(CH0_FF_TXI_CLK) +X(CH1_FF_TXI_CLK) +X(CH0_FF_EBRD_CLK) +X(CH1_FF_EBRD_CLK) +X(CH0_FF_TX_D_0) +X(CH1_FF_TX_D_0) +X(CH0_FF_TX_D_1) +X(CH1_FF_TX_D_1) +X(CH0_FF_TX_D_2) +X(CH1_FF_TX_D_2) +X(CH0_FF_TX_D_3) +X(CH1_FF_TX_D_3) +X(CH0_FF_TX_D_4) +X(CH1_FF_TX_D_4) +X(CH0_FF_TX_D_5) +X(CH1_FF_TX_D_5) +X(CH0_FF_TX_D_6) +X(CH1_FF_TX_D_6) +X(CH0_FF_TX_D_7) +X(CH1_FF_TX_D_7) +X(CH0_FF_TX_D_8) +X(CH1_FF_TX_D_8) +X(CH0_FF_TX_D_9) +X(CH1_FF_TX_D_9) +X(CH0_FF_TX_D_10) +X(CH1_FF_TX_D_10) +X(CH0_FF_TX_D_11) +X(CH1_FF_TX_D_11) +X(CH0_FF_TX_D_12) +X(CH1_FF_TX_D_12) +X(CH0_FF_TX_D_13) +X(CH1_FF_TX_D_13) +X(CH0_FF_TX_D_14) +X(CH1_FF_TX_D_14) +X(CH0_FF_TX_D_15) +X(CH1_FF_TX_D_15) +X(CH0_FF_TX_D_16) +X(CH1_FF_TX_D_16) +X(CH0_FF_TX_D_17) +X(CH1_FF_TX_D_17) +X(CH0_FF_TX_D_18) +X(CH1_FF_TX_D_18) +X(CH0_FF_TX_D_19) +X(CH1_FF_TX_D_19) +X(CH0_FF_TX_D_20) +X(CH1_FF_TX_D_20) +X(CH0_FF_TX_D_21) +X(CH1_FF_TX_D_21) +X(CH0_FF_TX_D_22) +X(CH1_FF_TX_D_22) +X(CH0_FF_TX_D_23) +X(CH1_FF_TX_D_23) +X(CH0_FFC_EI_EN) +X(CH1_FFC_EI_EN) +X(CH0_FFC_PCIE_DET_EN) +X(CH1_FFC_PCIE_DET_EN) +X(CH0_FFC_PCIE_CT) +X(CH1_FFC_PCIE_CT) +X(CH0_FFC_SB_INV_RX) +X(CH1_FFC_SB_INV_RX) +X(CH0_FFC_ENABLE_CGALIGN) +X(CH1_FFC_ENABLE_CGALIGN) +X(CH0_FFC_SIGNAL_DETECT) +X(CH1_FFC_SIGNAL_DETECT) +X(CH0_FFC_FB_LOOPBACK) +X(CH1_FFC_FB_LOOPBACK) +X(CH0_FFC_SB_PFIFO_LP) +X(CH1_FFC_SB_PFIFO_LP) +X(CH0_FFC_PFIFO_CLR) +X(CH1_FFC_PFIFO_CLR) +X(CH0_FFC_RATE_MODE_RX) +X(CH1_FFC_RATE_MODE_RX) +X(CH0_FFC_RATE_MODE_TX) +X(CH1_FFC_RATE_MODE_TX) +X(CH0_FFC_DIV11_MODE_RX) +X(CH1_FFC_DIV11_MODE_RX) +X(CH0_FFC_RX_GEAR_MODE) +X(CH1_FFC_RX_GEAR_MODE) +X(CH0_FFC_TX_GEAR_MODE) +X(CH1_FFC_TX_GEAR_MODE) +X(CH0_FFC_DIV11_MODE_TX) +X(CH1_FFC_DIV11_MODE_TX) +X(CH0_FFC_LDR_CORE2TX_EN) +X(CH1_FFC_LDR_CORE2TX_EN) +X(CH0_FFC_LANE_TX_RST) +X(CH1_FFC_LANE_TX_RST) +X(CH0_FFC_LANE_RX_RST) +X(CH1_FFC_LANE_RX_RST) +X(CH0_FFC_RRST) +X(CH1_FFC_RRST) +X(CH0_FFC_TXPWDNB) +X(CH1_FFC_TXPWDNB) +X(CH0_FFC_RXPWDNB) +X(CH1_FFC_RXPWDNB) +X(CH0_LDR_CORE2TX) +X(CH1_LDR_CORE2TX) +X(D_SCIWDATA0) +X(D_SCIWDATA1) +X(D_SCIWDATA2) +X(D_SCIWDATA3) +X(D_SCIWDATA4) +X(D_SCIWDATA5) +X(D_SCIWDATA6) +X(D_SCIWDATA7) +X(D_SCIADDR0) +X(D_SCIADDR1) +X(D_SCIADDR2) +X(D_SCIADDR3) +X(D_SCIADDR4) +X(D_SCIADDR5) +X(D_SCIENAUX) +X(D_SCISELAUX) +X(CH0_SCIEN) +X(CH1_SCIEN) +X(CH0_SCISEL) +X(CH1_SCISEL) +X(D_SCIRD) +X(D_SCIWSTN) +X(D_CYAWSTN) +X(D_FFC_SYNC_TOGGLE) +X(D_FFC_DUAL_RST) +X(D_FFC_MACRO_RST) +X(D_FFC_MACROPDB) +X(D_FFC_TRST) +X(CH0_FFC_CDR_EN_BITSLIP) +X(CH1_FFC_CDR_EN_BITSLIP) +X(D_SCAN_ENABLE) +X(D_SCAN_IN_0) +X(D_SCAN_IN_1) +X(D_SCAN_IN_2) +X(D_SCAN_IN_3) +X(D_SCAN_IN_4) +X(D_SCAN_IN_5) +X(D_SCAN_IN_6) +X(D_SCAN_IN_7) +X(D_SCAN_MODE) +X(D_SCAN_RESET) +X(D_CIN0) +X(D_CIN1) +X(D_CIN2) +X(D_CIN3) +X(D_CIN4) +X(D_CIN5) +X(D_CIN6) +X(D_CIN7) +X(D_CIN8) +X(D_CIN9) +X(D_CIN10) +X(D_CIN11) +X(CH0_HDOUTP) +X(CH1_HDOUTP) +X(CH0_HDOUTN) +X(CH1_HDOUTN) +X(D_TXBIT_CLKP_TO_ND) +X(D_TXBIT_CLKN_TO_ND) +X(D_SYNC_PULSE2ND) +X(D_TXPLL_LOL_TO_ND) +X(CH0_FF_RX_F_CLK) +X(CH1_FF_RX_F_CLK) +X(CH0_FF_RX_H_CLK) +X(CH1_FF_RX_H_CLK) +X(CH0_FF_TX_F_CLK) +X(CH1_FF_TX_F_CLK) +X(CH0_FF_TX_H_CLK) +X(CH1_FF_TX_H_CLK) +X(CH0_FF_RX_PCLK) +X(CH1_FF_RX_PCLK) +X(CH0_FF_TX_PCLK) +X(CH1_FF_TX_PCLK) +X(CH0_FF_RX_D_0) +X(CH1_FF_RX_D_0) +X(CH0_FF_RX_D_1) +X(CH1_FF_RX_D_1) +X(CH0_FF_RX_D_2) +X(CH1_FF_RX_D_2) +X(CH0_FF_RX_D_3) +X(CH1_FF_RX_D_3) +X(CH0_FF_RX_D_4) +X(CH1_FF_RX_D_4) +X(CH0_FF_RX_D_5) +X(CH1_FF_RX_D_5) +X(CH0_FF_RX_D_6) +X(CH1_FF_RX_D_6) +X(CH0_FF_RX_D_7) +X(CH1_FF_RX_D_7) +X(CH0_FF_RX_D_8) +X(CH1_FF_RX_D_8) +X(CH0_FF_RX_D_9) +X(CH1_FF_RX_D_9) +X(CH0_FF_RX_D_10) +X(CH1_FF_RX_D_10) +X(CH0_FF_RX_D_11) +X(CH1_FF_RX_D_11) +X(CH0_FF_RX_D_12) +X(CH1_FF_RX_D_12) +X(CH0_FF_RX_D_13) +X(CH1_FF_RX_D_13) +X(CH0_FF_RX_D_14) +X(CH1_FF_RX_D_14) +X(CH0_FF_RX_D_15) +X(CH1_FF_RX_D_15) +X(CH0_FF_RX_D_16) +X(CH1_FF_RX_D_16) +X(CH0_FF_RX_D_17) +X(CH1_FF_RX_D_17) +X(CH0_FF_RX_D_18) +X(CH1_FF_RX_D_18) +X(CH0_FF_RX_D_19) +X(CH1_FF_RX_D_19) +X(CH0_FF_RX_D_20) +X(CH1_FF_RX_D_20) +X(CH0_FF_RX_D_21) +X(CH1_FF_RX_D_21) +X(CH0_FF_RX_D_22) +X(CH1_FF_RX_D_22) +X(CH0_FF_RX_D_23) +X(CH1_FF_RX_D_23) +X(CH0_FFS_PCIE_DONE) +X(CH1_FFS_PCIE_DONE) +X(CH0_FFS_PCIE_CON) +X(CH1_FFS_PCIE_CON) +X(CH0_FFS_RLOS) +X(CH1_FFS_RLOS) +X(CH0_FFS_LS_SYNC_STATUS) +X(CH1_FFS_LS_SYNC_STATUS) +X(CH0_FFS_CC_UNDERRUN) +X(CH1_FFS_CC_UNDERRUN) +X(CH0_FFS_CC_OVERRUN) +X(CH1_FFS_CC_OVERRUN) +X(CH0_FFS_RXFBFIFO_ERROR) +X(CH1_FFS_RXFBFIFO_ERROR) +X(CH0_FFS_TXFBFIFO_ERROR) +X(CH1_FFS_TXFBFIFO_ERROR) +X(CH0_FFS_RLOL) +X(CH1_FFS_RLOL) +X(CH0_FFS_SKP_ADDED) +X(CH1_FFS_SKP_ADDED) +X(CH0_FFS_SKP_DELETED) +X(CH1_FFS_SKP_DELETED) +X(CH0_LDR_RX2CORE) +X(CH1_LDR_RX2CORE) +X(D_SCIRDATA0) +X(D_SCIRDATA1) +X(D_SCIRDATA2) +X(D_SCIRDATA3) +X(D_SCIRDATA4) +X(D_SCIRDATA5) +X(D_SCIRDATA6) +X(D_SCIRDATA7) +X(D_SCIINT) +X(D_SCAN_OUT_0) +X(D_SCAN_OUT_1) +X(D_SCAN_OUT_2) +X(D_SCAN_OUT_3) +X(D_SCAN_OUT_4) +X(D_SCAN_OUT_5) +X(D_SCAN_OUT_6) +X(D_SCAN_OUT_7) +X(D_COUT0) +X(D_COUT1) +X(D_COUT2) +X(D_COUT3) +X(D_COUT4) +X(D_COUT5) +X(D_COUT6) +X(D_COUT7) +X(D_COUT8) +X(D_COUT9) +X(D_COUT10) +X(D_COUT11) +X(D_COUT12) +X(D_COUT13) +X(D_COUT14) +X(D_COUT15) +X(D_COUT16) +X(D_COUT17) +X(D_COUT18) +X(D_COUT19) +X(D_REFCLKI) +X(D_FFS_PLOL) + +X(PCSCLKDIV) +X(SEL2) +X(SEL1) +X(SEL0) +X(CDIV1) +X(CDIVX)
\ No newline at end of file |