diff options
| -rw-r--r-- | common/nextpnr.h | 10 | ||||
| -rw-r--r-- | common/placer1.cc | 8 | ||||
| -rw-r--r-- | ecp5/arch_pybindings.cc | 125 | ||||
| -rw-r--r-- | ecp5/bitstream.cc | 35 | ||||
| -rw-r--r-- | generic/arch_pybindings.cc | 12 | ||||
| -rw-r--r-- | gui/designwidget.cc | 2 | ||||
| -rw-r--r-- | ice40/arch.h | 12 | ||||
| -rw-r--r-- | ice40/arch_place.cc | 8 | ||||
| -rw-r--r-- | ice40/pack.cc | 81 | ||||
| -rwxr-xr-x | ice40/picorv32_benchmark.py | 43 |
10 files changed, 308 insertions, 28 deletions
diff --git a/common/nextpnr.h b/common/nextpnr.h index 2eb46bd3..f391469c 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -273,6 +273,16 @@ struct CellInfo : ArchCellInfo // cell_port -> bel_pin std::unordered_map<IdString, IdString> pins; + + // placement constraints + CellInfo *constr_parent; + std::vector<CellInfo*> constr_children; + const int UNCONSTR = INT_MIN; + int constr_x = UNCONSTR; // this.x - parent.x + int constr_y = UNCONSTR; // this.y - parent.y + int constr_z = UNCONSTR; // this.z - parent.z + bool constr_abs_z = false; // parent.z := 0 + // parent.[xyz] := 0 when (constr_parent == nullptr) }; struct DeterministicRNG diff --git a/common/placer1.cc b/common/placer1.cc index f713fb88..4659da11 100644 --- a/common/placer1.cc +++ b/common/placer1.cc @@ -94,7 +94,13 @@ class SAPlacer BelType bel_type = ctx->getBelType(bel); if (bel_type != ctx->belTypeFromId(cell->type)) { log_error("Bel \'%s\' of type \'%s\' does not match cell " - "\'%s\' of type \'%s\'", + "\'%s\' of type \'%s\'\n", + loc_name.c_str(), ctx->belTypeToId(bel_type).c_str(ctx), cell->name.c_str(ctx), + cell->type.c_str(ctx)); + } + if (!ctx->isValidBelForCell(cell, bel)) { + log_error("Bel \'%s\' of type \'%s\' is not valid for cell " + "\'%s\' of type \'%s\'\n", loc_name.c_str(), ctx->belTypeToId(bel_type).c_str(ctx), cell->name.c_str(ctx), cell->type.c_str(ctx)); } diff --git a/ecp5/arch_pybindings.cc b/ecp5/arch_pybindings.cc index 8310c3a1..c261c3ec 100644 --- a/ecp5/arch_pybindings.cc +++ b/ecp5/arch_pybindings.cc @@ -2,7 +2,7 @@ * nextpnr -- Next Generation Place and Route * * Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com> - * Copyright (C) 2018 David Shah <dave@ds0.me> + * Copyright (C) 2018 David Shah <david@symbioticeda.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -20,13 +20,132 @@ #ifndef NO_PYTHON +#include "arch_pybindings.h" #include "nextpnr.h" #include "pybindings.h" NEXTPNR_NAMESPACE_BEGIN -void arch_wrap_python() {} +void arch_wrap_python() +{ + using namespace PythonConversion; + class_<ArchArgs>("ArchArgs").def_readwrite("type", &ArchArgs::type); + + class_<BelId>("BelId").def_readwrite("index", &BelId::index); + + class_<WireId>("WireId").def_readwrite("index", &WireId::index); + + class_<PipId>("PipId").def_readwrite("index", &PipId::index); + + class_<BelPin>("BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin); + + enum_<PortPin>("PortPin") +#define X(t) .value("PIN_" #t, PIN_##t) + +#include "portpins.inc" + ; +#undef X + + auto arch_cls = class_<Arch, Arch *, bases<BaseCtx>, boost::noncopyable>("Arch", init<ArchArgs>()); + auto ctx_cls = class_<Context, Context *, bases<Arch>, boost::noncopyable>("Context", no_init) + .def("checksum", &Context::checksum) + .def("pack", &Context::pack) + .def("place", &Context::place) + .def("route", &Context::route); + + fn_wrapper_1a<Context, decltype(&Context::getBelType), &Context::getBelType, conv_to_str<BelType>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelType"); + fn_wrapper_1a<Context, decltype(&Context::checkBelAvail), &Context::checkBelAvail, pass_through<bool>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "checkBelAvail"); + fn_wrapper_1a<Context, decltype(&Context::getBelChecksum), &Context::getBelChecksum, pass_through<uint32_t>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelChecksum"); + fn_wrapper_3a_v<Context, decltype(&Context::bindBel), &Context::bindBel, conv_from_str<BelId>, + conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindBel"); + fn_wrapper_1a_v<Context, decltype(&Context::unbindBel), &Context::unbindBel, conv_from_str<BelId>>::def_wrap( + ctx_cls, "unbindBel"); + fn_wrapper_1a<Context, decltype(&Context::getBoundBelCell), &Context::getBoundBelCell, conv_to_str<IdString>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBoundBelCell"); + fn_wrapper_1a<Context, decltype(&Context::getConflictingBelCell), &Context::getConflictingBelCell, + conv_to_str<IdString>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell"); + fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, wrap_context<BelRange>>::def_wrap(ctx_cls, + "getBels"); + + fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>, + conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire"); + fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins, wrap_context<BelPinRange>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireBelPins"); + + fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum"); + fn_wrapper_3a_v<Context, decltype(&Context::bindWire), &Context::bindWire, conv_from_str<WireId>, + conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindWire"); + fn_wrapper_1a_v<Context, decltype(&Context::unbindWire), &Context::unbindWire, conv_from_str<WireId>>::def_wrap( + ctx_cls, "unbindWire"); + fn_wrapper_1a<Context, decltype(&Context::checkWireAvail), &Context::checkWireAvail, pass_through<bool>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "checkWireAvail"); + fn_wrapper_1a<Context, decltype(&Context::getBoundWireNet), &Context::getBoundWireNet, conv_to_str<IdString>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getBoundWireNet"); + fn_wrapper_1a<Context, decltype(&Context::getConflictingWireNet), &Context::getConflictingWireNet, + conv_to_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getConflictingWireNet"); + + fn_wrapper_0a<Context, decltype(&Context::getWires), &Context::getWires, wrap_context<WireRange>>::def_wrap( + ctx_cls, "getWires"); + + fn_wrapper_0a<Context, decltype(&Context::getPips), &Context::getPips, wrap_context<AllPipRange>>::def_wrap( + ctx_cls, "getPips"); + fn_wrapper_1a<Context, decltype(&Context::getPipChecksum), &Context::getPipChecksum, pass_through<uint32_t>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipChecksum"); + fn_wrapper_3a_v<Context, decltype(&Context::bindPip), &Context::bindPip, conv_from_str<PipId>, + conv_from_str<IdString>, pass_through<PlaceStrength>>::def_wrap(ctx_cls, "bindPip"); + fn_wrapper_1a_v<Context, decltype(&Context::unbindPip), &Context::unbindPip, conv_from_str<PipId>>::def_wrap( + ctx_cls, "unbindPip"); + fn_wrapper_1a<Context, decltype(&Context::checkPipAvail), &Context::checkPipAvail, pass_through<bool>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "checkPipAvail"); + fn_wrapper_1a<Context, decltype(&Context::getBoundPipNet), &Context::getBoundPipNet, conv_to_str<IdString>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getBoundPipNet"); + fn_wrapper_1a<Context, decltype(&Context::getConflictingPipNet), &Context::getConflictingPipNet, + conv_to_str<IdString>, conv_from_str<PipId>>::def_wrap(ctx_cls, "getConflictingPipNet"); + + fn_wrapper_1a<Context, decltype(&Context::getPipsDownhill), &Context::getPipsDownhill, wrap_context<PipRange>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsDownhill"); + fn_wrapper_1a<Context, decltype(&Context::getPipsUphill), &Context::getPipsUphill, wrap_context<PipRange>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getPipsUphill"); + fn_wrapper_1a<Context, decltype(&Context::getWireAliases), &Context::getWireAliases, wrap_context<PipRange>, + conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireAliases"); + + fn_wrapper_1a<Context, decltype(&Context::getPipSrcWire), &Context::getPipSrcWire, conv_to_str<WireId>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipSrcWire"); + fn_wrapper_1a<Context, decltype(&Context::getPipDstWire), &Context::getPipDstWire, conv_to_str<WireId>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDstWire"); + fn_wrapper_1a<Context, decltype(&Context::getPipDelay), &Context::getPipDelay, pass_through<DelayInfo>, + conv_from_str<PipId>>::def_wrap(ctx_cls, "getPipDelay"); + + fn_wrapper_1a<Context, decltype(&Context::getPackagePinBel), &Context::getPackagePinBel, conv_to_str<BelId>, + pass_through<std::string>>::def_wrap(ctx_cls, "getPackagePinBel"); + fn_wrapper_1a<Context, decltype(&Context::getBelPackagePin), &Context::getBelPackagePin, pass_through<std::string>, + conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelPackagePin"); + + fn_wrapper_0a<Context, decltype(&Context::getChipName), &Context::getChipName, pass_through<std::string>>::def_wrap( + ctx_cls, "getChipName"); + fn_wrapper_0a<Context, decltype(&Context::archId), &Context::archId, conv_to_str<IdString>>::def_wrap(ctx_cls, + "archId"); + + typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap; + typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap; + + readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_context<CellMap &>>::def_wrap(ctx_cls, + "cells"); + readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls, + "nets"); + WRAP_RANGE(Bel, conv_to_str<BelId>); + WRAP_RANGE(Wire, conv_to_str<WireId>); + WRAP_RANGE(AllPip, conv_to_str<PipId>); + WRAP_RANGE(Pip, conv_to_str<PipId>); + + WRAP_MAP_UPTR(CellMap, "IdCellMap"); + WRAP_MAP_UPTR(NetMap, "IdNetMap"); +} NEXTPNR_NAMESPACE_END -#endif +#endif // NO_PYTHON diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index c2218762..f1feba24 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -185,22 +185,31 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex } // Find bank voltages std::unordered_map<int, IOVoltage> bankVcc; + std::unordered_map<int, bool> bankLvds; + for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) { int bank = ctx->getPioBelBank(ci->bel); + std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT"); std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33"); - IOVoltage vcc = get_vccio(ioType_from_str(iotype)); - if (bankVcc.find(bank) != bankVcc.end()) { - // TODO: strong and weak constraints - if (bankVcc[bank] != vcc) { - log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.", - cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(), - iovoltage_to_str(vcc).c_str(), bank); + + if (dir != "INPUT") { + IOVoltage vcc = get_vccio(ioType_from_str(iotype)); + if (bankVcc.find(bank) != bankVcc.end()) { + // TODO: strong and weak constraints + if (bankVcc[bank] != vcc) { + log_error("Error processing '%s': incompatible IO voltages %s and %s on bank %d.", + cell.first.c_str(ctx), iovoltage_to_str(bankVcc[bank]).c_str(), + iovoltage_to_str(vcc).c_str(), bank); + } + } else { + bankVcc[bank] = vcc; } - } else { - bankVcc[bank] = vcc; } + + if (iotype == "LVDS") + bankLvds[bank] = true; } } @@ -211,6 +220,10 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex int bank = std::stoi(type.substr(7)); if (bankVcc.find(bank) != bankVcc.end()) cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank])); + if (bankLvds[bank]) { + cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON"); + cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON"); + } } } @@ -267,8 +280,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex other = "PIOD"; else log_error("cannot place differential IO at location %s\n", pio.c_str()); - cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); - cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); + //cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); + //cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_"); cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE"); cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE"); } diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc index a99723f2..186b2c13 100644 --- a/generic/arch_pybindings.cc +++ b/generic/arch_pybindings.cc @@ -20,12 +20,22 @@ #ifndef NO_PYTHON +#include "arch_pybindings.h" #include "nextpnr.h" #include "pybindings.h" NEXTPNR_NAMESPACE_BEGIN -void arch_wrap_python() { class_<ArchArgs>("ArchArgs"); } +void arch_wrap_python() +{ + using namespace PythonConversion; + auto arch_cls = class_<Arch, Arch *, bases<BaseCtx>, boost::noncopyable>("Arch", init<ArchArgs>()); + auto ctx_cls = class_<Context, Context *, bases<Arch>, boost::noncopyable>("Context", no_init) + .def("checksum", &Context::checksum) + .def("pack", &Context::pack) + .def("place", &Context::place) + .def("route", &Context::route); +} NEXTPNR_NAMESPACE_END diff --git a/gui/designwidget.cc b/gui/designwidget.cc index e63ee937..7e8e2840 100644 --- a/gui/designwidget.cc +++ b/gui/designwidget.cc @@ -312,6 +312,7 @@ void DesignWidget::newContext(Context *ctx) QMap<QString, QTreeWidgetItem *> pip_items;
pip_root->setText(0, "Pips");
treeWidget->insertTopLevelItem(0, pip_root);
+#ifndef ARCH_ECP5
if (ctx) {
for (auto pip : ctx->getPips()) {
auto id = ctx->getPipName(pip);
@@ -338,6 +339,7 @@ void DesignWidget::newContext(Context *ctx) for (auto pip : nameToItem[2].toStdMap()) {
pip_root->addChild(pip.second);
}
+#endif
nets_root = new QTreeWidgetItem(treeWidget);
nets_root->setText(0, "Nets");
diff --git a/ice40/arch.h b/ice40/arch.h index 3aec25a2..bd937371 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -739,6 +739,18 @@ struct Arch : BaseCtx IdString id_cen, id_clk, id_sr; IdString id_i0, id_i1, id_i2, id_i3; IdString id_dff_en, id_neg_clk; + + // ------------------------------------------------- + BelPin getIOBSharingPLLPin(BelId pll, PortPin pll_pin) const + { + auto wire = getBelPinWire(pll, pll_pin); + for (auto src_bel : getWireBelPins(wire)) { + if (getBelType(src_bel.bel) == TYPE_SB_IO && src_bel.pin == PIN_D_IN_0) { + return src_bel; + } + } + NPNR_ASSERT_FALSE("Expected PLL pin to share an output with an SB_IO D_IN_{0,1}"); + } }; NEXTPNR_NAMESPACE_END diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 59e1807d..b3404d6c 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -124,12 +124,16 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const } // Is there a PLL that shares this IO buffer? if (pll_bel.index != -1) { + auto pll_cell = getBoundBelCell(pll_bel); // Is a PLL placed in this PLL bel? - if (!checkBelAvail(pll_bel)) { + if (pll_cell != IdString()) { // Is the shared port driving a net? - auto pll_cell = getBoundBelCell(pll_bel); auto pi = cells.at(pll_cell)->ports[portPinToId(pll_bel_pin)]; if (pi.net != nullptr) { + // Are we perhaps a PAD INPUT Bel that can be placed here? + if (cells.at(pll_cell)->attrs[id("BEL_PAD_INPUT")] == getBelName(bel).str(this)) { + return true; + } return false; } } diff --git a/ice40/pack.cc b/ice40/pack.cc index b4f711f3..91dcf846 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -550,13 +550,13 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString NPNR_ASSERT(port.net != nullptr); // Create pass-through LUT. - std::unique_ptr<CellInfo> pt = - create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "$nextpnr_ice40_pack_pll_lc"); - pt->params[ctx->id("LUT_INIT")] = "255"; // output is always I3 + std::unique_ptr<CellInfo> pt = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), + ci->name.str(ctx) + "$nextpnr_" + portId.str(ctx) + "_lut_through"); + pt->params[ctx->id("LUT_INIT")] = "65280"; // output is always I3 // Create LUT output net. std::unique_ptr<NetInfo> out_net = std::unique_ptr<NetInfo>(new NetInfo); - out_net->name = ctx->id(ci->name.str(ctx) + "$nextnr_ice40_pack_pll_net"); + out_net->name = ctx->id(ci->name.str(ctx) + "$nextnr_" + portId.str(ctx) + "_lut_through_net"); out_net->driver.cell = pt.get(); out_net->driver.port = ctx->id("O"); pt->ports.at(ctx->id("O")).net = out_net.get(); @@ -647,16 +647,14 @@ static void pack_special(Context *ctx) } new_cells.push_back(std::move(packed)); } else if (is_sb_pll40(ctx, ci)) { + bool is_pad = is_sb_pll40_pad(ctx, ci); + bool is_core = !is_pad; + std::unique_ptr<CellInfo> packed = create_ice_cell(ctx, ctx->id("ICESTORM_PLL"), ci->name.str(ctx) + "_PLL"); + packed->attrs[ctx->id("TYPE")] = ci->type.str(ctx); packed_cells.insert(ci->name); - if (is_sb_pll40_pad(ctx, ci)) { - // TODO(q3k): Implement these after checking their behaviour on - // a board with exposed 'clock pads'. - log_error("SB_PLL40_*_PAD cells are not supported yet.\n"); - } - for (auto attr : ci->attrs) packed->attrs[attr.first] = attr.second; for (auto param : ci->params) @@ -672,6 +670,8 @@ static void pack_special(Context *ctx) : feedback_path == "EXTERNAL" ? "6" : feedback_path; packed->params[ctx->id("PLLTYPE")] = std::to_string(sb_pll40_type(ctx, ci)); + NetInfo *pad_packagepin_net = nullptr; + for (auto port : ci->ports) { PortInfo &pi = port.second; std::string newname = pi.name.str(ctx); @@ -685,6 +685,22 @@ static void pack_special(Context *ctx) newname = "PLLOUT_B"; if (pi.name == ctx->id("PLLOUTCORE")) newname = "PLLOUT_A"; + + if (pi.name == ctx->id("PACKAGEPIN")) { + if (!is_pad) { + log_error(" PLL '%s' has a PACKAGEPIN but is not a PAD PLL", ci->name.c_str(ctx)); + } else { + // We drop this port and instead place the PLL adequately below. + pad_packagepin_net = port.second.net; + NPNR_ASSERT(pad_packagepin_net != nullptr); + continue; + } + } + if (pi.name == ctx->id("REFERENCECLK")) { + if (!is_core) + log_error(" PLL '%s' has a REFERENCECLK but is not a CORE PLL", ci->name.c_str(ctx)); + } + replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname)); } @@ -696,6 +712,42 @@ static void pack_special(Context *ctx) for (auto bel : ctx->getBels()) { if (ctx->getBelType(bel) != TYPE_ICESTORM_PLL) continue; + + // A PAD PLL must have its' PACKAGEPIN on the SB_IO that's shared + // with PLLOUT_A. + if (is_pad) { + auto pll_sb_io_belpin = ctx->getIOBSharingPLLPin(bel, PIN_PLLOUT_A); + NPNR_ASSERT(pad_packagepin_net != nullptr); + auto pll_packagepin_driver = pad_packagepin_net->driver; + NPNR_ASSERT(pll_packagepin_driver.cell != nullptr); + if (pll_packagepin_driver.cell->type != ctx->id("SB_IO")) { + log_error(" PLL '%s' has a PACKAGEPIN driven by " + "an %s, should be directly connected to an input SB_IO\n", + ci->name.c_str(ctx), pll_packagepin_driver.cell->type.c_str(ctx)); + } + + auto packagepin_cell = pll_packagepin_driver.cell; + auto packagepin_bel_name = packagepin_cell->attrs.find(ctx->id("BEL")); + if (packagepin_bel_name == packagepin_cell->attrs.end()) { + log_error(" PLL '%s' PACKAGEPIN SB_IO '%s' is unconstrained\n", ci->name.c_str(ctx), + packagepin_cell->name.c_str(ctx)); + } + auto packagepin_bel = ctx->getBelByName(ctx->id(packagepin_bel_name->second)); + if (pll_sb_io_belpin.bel != packagepin_bel) { + log_error(" PLL '%s' PACKAGEPIN is connected to pin %s, can only be pin %s\n", + ci->name.c_str(ctx), ctx->getBelPackagePin(packagepin_bel).c_str(), + ctx->getBelPackagePin(pll_sb_io_belpin.bel).c_str()); + } + if (pad_packagepin_net->users.size() != 1) { + log_error(" PLL '%s' clock input '%s' can only drive PLL\n", ci->name.c_str(ctx), + pad_packagepin_net->name.c_str(ctx)); + } + // Set an attribute about this PLL's PAD SB_IO. + packed->attrs[ctx->id("BEL_PAD_INPUT")] = packagepin_bel_name->second; + // Remove the connection from the SB_IO to the PLL. + packagepin_cell->ports.erase(pll_packagepin_driver.port); + } + log_info(" constrained '%s' to %s\n", packed->name.c_str(ctx), ctx->getBelName(bel).c_str(ctx)); packed->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx); pll_bel = bel; @@ -706,6 +758,15 @@ static void pack_special(Context *ctx) } } + // Delete the original PACKAGEPIN net if needed. + if (pad_packagepin_net != nullptr) { + for (auto user : pad_packagepin_net->users) { + user.cell->ports.erase(user.port); + } + ctx->nets.erase(pad_packagepin_net->name); + pad_packagepin_net = nullptr; + } + // The LOCK signal on iCE40 PLLs goes through the neigh_op_bnl_1 wire. // In practice, this means the LOCK signal can only directly reach LUT // inputs. diff --git a/ice40/picorv32_benchmark.py b/ice40/picorv32_benchmark.py new file mode 100755 index 00000000..9544db50 --- /dev/null +++ b/ice40/picorv32_benchmark.py @@ -0,0 +1,43 @@ +#!/usr/bin/env python3 +import os, sys, threading +from os import path +import subprocess +import re + +num_runs = 8 + +if not path.exists("picorv32.json"): + os.remove("picorv32.json") + subprocess.run(["wget", "https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v"], check=True) + subprocess.run(["yosys", "-q", "-p", "synth_ice40 -json picorv32.json -top top", "picorv32.v", "picorv32_top.v"], check=True) + +fmax = {} + +if not path.exists("picorv32_work"): + os.mkdir("picorv32_work") + +threads = [] + +for i in range(num_runs): + def runner(run): + ascfile = "picorv32_work/picorv32_s{}.asc".format(run) + if path.exists(ascfile): + os.remove(ascfile) + result = subprocess.run(["../nextpnr-ice40", "--hx8k", "--seed", str(run), "--json", "picorv32.json", "--asc", ascfile], stderr=subprocess.DEVNULL, stdout=subprocess.DEVNULL) + if result.returncode != 0: + print("Run {} failed!".format(run)) + else: + icetime_res = subprocess.check_output(["icetime", "-d", "hx8k", ascfile]) + fmax_m = re.search(r'\(([0-9.]+) MHz\)', icetime_res.decode('utf-8')) + fmax[run] = float(fmax_m.group(1)) + threads.append(threading.Thread(target=runner, args=[i+1])) + +for t in threads: t.start() +for t in threads: t.join() + +fmax_min = min(fmax.values()) +fmax_max = max(fmax.values()) +fmax_avg = sum(fmax.values()) / len(fmax) + +print("{}/{} runs passed".format(len(fmax), num_runs)) +print("icetime: min = {} MHz, avg = {} MHz, max = {} MHz".format(fmax_min, fmax_avg, fmax_max)) |