diff options
| -rw-r--r-- | ice40/arch.h | 4 | ||||
| -rw-r--r-- | ice40/chipdb.py | 30 | 
2 files changed, 0 insertions, 34 deletions
| diff --git a/ice40/arch.h b/ice40/arch.h index d4d71cfc..3f6a5324 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -83,10 +83,6 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {      int32_t num_uphill, num_downhill;      RelPtr<int32_t> pips_uphill, pips_downhill; -    int32_t num_bels_downhill; -    BelPortPOD bel_uphill; -    RelPtr<BelPortPOD> bels_downhill; -      int32_t num_bel_pins;      RelPtr<BelPortPOD> bel_pins; diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 4dcddbed..1127767d 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -41,8 +41,6 @@ extra_cells = dict()  extra_cell_config = dict()  packages = list() -wire_uphill_belport = dict() -wire_downhill_belports = dict()  wire_belports = dict()  wire_names = dict() @@ -451,17 +449,12 @@ for i in range(8):      add_wire(0, 0, "padin_%d" % i)  def add_bel_input(bel, wire, port): -    if wire not in wire_downhill_belports: -        wire_downhill_belports[wire] = set() -    wire_downhill_belports[wire].add((bel, port))      if wire not in wire_belports:          wire_belports[wire] = set()      wire_belports[wire].add((bel, port))      bel_wires[bel].append((wire, port, 0))  def add_bel_output(bel, wire, port): -    assert wire not in wire_uphill_belport -    wire_uphill_belport[wire] = (bel, port)      if wire not in wire_belports:          wire_belports[wire] = set()      wire_belports[wire].add((bel, port)) @@ -1001,15 +994,6 @@ for wire in range(num_wires):          num_downhill = 0          list_downhill = None -    if wire in wire_downhill_belports: -        num_bels_downhill = len(wire_downhill_belports[wire]) -        bba.l("wire%d_downbels" % wire, "BelPortPOD") -        for belport in sorted(wire_downhill_belports[wire]): -            bba.u32(belport[0], "bel_index") -            bba.u32(portpins[belport[1]], "port") -    else: -        num_bels_downhill = 0 -      if wire in wire_belports:          num_bel_pins = len(wire_belports[wire])          bba.l("wire%d_bels" % wire, "BelPortPOD") @@ -1028,19 +1012,9 @@ for wire in range(num_wires):      info["num_downhill"] = num_downhill      info["list_downhill"] = list_downhill -    info["num_bels_downhill"] = num_bels_downhill -    info["list_bels_downhill"] = ("wire%d_downbels" % wire) if num_bels_downhill > 0 else None -      info["num_bel_pins"] = num_bel_pins      info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None -    if wire in wire_uphill_belport: -        info["uphill_bel"] = wire_uphill_belport[wire][0] -        info["uphill_pin"] = portpins[wire_uphill_belport[wire][1]] -    else: -        info["uphill_bel"] = -1 -        info["uphill_pin"] = 0 -      avg_x, avg_y = 0, 0      if wire in wire_xy:          for x, y in wire_xy[wire]: @@ -1115,10 +1089,6 @@ for wire, info in enumerate(wireinfo):      bba.u32(info["num_downhill"], "num_downhill")      bba.r(info["list_uphill"], "pips_uphill")      bba.r(info["list_downhill"], "pips_downhill") -    bba.u32(info["num_bels_downhill"], "num_bels_downhill") -    bba.u32(info["uphill_bel"], "bel_uphill.bel_index") -    bba.u32(info["uphill_pin"], "bel_uphill.port") -    bba.r(info["list_bels_downhill"], "bels_downhill")      bba.u32(info["num_bel_pins"], "num_bel_pins")      bba.r(info["list_bel_pins"], "bel_pins")      bba.u32(len(wire_segments[wire]), "num_segments") | 
