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-rw-r--r--ecp5/bitstream.cc3
-rw-r--r--gowin/arch.cc27
-rw-r--r--gowin/arch.h23
-rw-r--r--gowin/arch_pybindings.cc1
-rw-r--r--gowin/cells.cc2
-rw-r--r--gowin/main.cc2
-rw-r--r--gowin/pack.cc22
7 files changed, 37 insertions, 43 deletions
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index c6863cd6..d668c8bc 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -870,7 +870,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (dir != "OUTPUT")
log_error("Pseudo-differential IO '%s' must be output\n", ctx->nameOf(ci));
if (pio != "PIOA")
- log_error("Pseudo-differential IO '%s' must be constrained to 'A' side of pair\n", ctx->nameOf(ci));
+ log_error("Pseudo-differential IO '%s' must be constrained to 'A' side of pair\n",
+ ctx->nameOf(ci));
std::string cpio_tile = get_comp_pio_tile(ctx, bel);
std::string cpic_tile = get_comp_pic_tile(ctx, bel);
cc.tiles[cpio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
diff --git a/gowin/arch.cc b/gowin/arch.cc
index 8b39cd27..b3a6a47d 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -479,28 +479,29 @@ DelayInfo Arch::getWireTypeDelay(IdString wire)
}
}
-void Arch::read_cst(std::istream &in) {
+void Arch::read_cst(std::istream &in)
+{
std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ;]+);");
std::smatch match;
std::string line;
while (!in.eof()) {
std::getline(in, line);
- if(!std::regex_match(line, match, iobre)) {
+ if (!std::regex_match(line, match, iobre)) {
// empty line or comment
- if(line.empty() || line.rfind("//", 0) == 0) {
+ if (line.empty() || line.rfind("//", 0) == 0) {
continue;
} else {
log_warning("Invalid constraint: %s\n", line.c_str());
continue;
}
}
- //std::cout << match[1] << " " << match[2] << std::endl;
+ // std::cout << match[1] << " " << match[2] << std::endl;
IdString net = id(match[1]);
IdString pinname = id(match[2]);
const PairPOD *belname = pairLookup(package->pins.get(), package->num_pins, pinname.index);
- if ( belname == nullptr)
+ if (belname == nullptr)
log_error("Pin %s not found\n", pinname.c_str(this));
- //BelId bel = getBelByName(belname->src_id);
+ // BelId bel = getBelByName(belname->src_id);
// for (auto cell : sorted(cells)) {
// std::cout << cell.first.str(this) << std::endl;
// }
@@ -545,10 +546,10 @@ Arch::Arch(ArchArgs args) : args(args)
if (speed == nullptr) {
log_error("Unsuported speed grade '%s'.\n", args.speed.c_str());
}
- const VariantPOD* variant = nullptr;
+ const VariantPOD *variant = nullptr;
for (unsigned int i = 0; i < db->num_variants; i++) {
auto var = &db->variants[i];
- //std::cout << IdString(var->name_id).str(this) << std::endl;
+ // std::cout << IdString(var->name_id).str(this) << std::endl;
if (IdString(var->name_id) == id(args.device)) {
variant = var;
break;
@@ -776,10 +777,7 @@ const std::vector<BelId> &Arch::getBelsByTile(int x, int y) const { return bels_
bool Arch::getBelGlobalBuf(BelId bel) const { return bels.at(bel).gb; }
-uint32_t Arch::getBelChecksum(BelId bel) const
-{
- return bel.index;
-}
+uint32_t Arch::getBelChecksum(BelId bel) const { return bel.index; }
void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
{
@@ -896,10 +894,7 @@ IdString Arch::getPipType(PipId pip) const { return pips.at(pip).type; }
const std::map<IdString, std::string> &Arch::getPipAttrs(PipId pip) const { return pips.at(pip).attrs; }
-uint32_t Arch::getPipChecksum(PipId wire) const
-{
- return wire.index;
-}
+uint32_t Arch::getPipChecksum(PipId wire) const { return wire.index; }
void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
{
diff --git a/gowin/arch.h b/gowin/arch.h
index 05c9e125..5591744d 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -35,7 +35,10 @@ template <typename T> struct RelPtr
const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
- T *get_mut() const { return const_cast<T *>(reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset)); }
+ T *get_mut() const
+ {
+ return const_cast<T *>(reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset));
+ }
const T &operator[](size_t index) const { return get()[index]; }
@@ -98,19 +101,19 @@ NPNR_PACKED_STRUCT(struct TimingGroupsPOD {
TimingGroupPOD alu;
TimingGroupPOD sram;
TimingGroupPOD dff;
- //TimingGroupPOD dl;
- //TimingGroupPOD iddroddr;
- //TimingGroupPOD pll;
- //TimingGroupPOD dll;
+ // TimingGroupPOD dl;
+ // TimingGroupPOD iddroddr;
+ // TimingGroupPOD pll;
+ // TimingGroupPOD dll;
TimingGroupPOD bram;
- //TimingGroupPOD dsp;
+ // TimingGroupPOD dsp;
TimingGroupPOD fanout;
TimingGroupPOD glbsrc;
TimingGroupPOD hclk;
TimingGroupPOD iodelay;
- //TimingGroupPOD io;
- //TimingGroupPOD iregoreg;
- TimingGroupPOD wire;
+ // TimingGroupPOD io;
+ // TimingGroupPOD iregoreg;
+ TimingGroupPOD wire;
});
NPNR_PACKED_STRUCT(struct TimingClassPOD {
@@ -300,7 +303,7 @@ struct Arch : BaseCtx
void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold);
void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq);
- IdString wireToGlobal(int &row, int &col, const DatabasePOD* db, IdString &wire);
+ IdString wireToGlobal(int &row, int &col, const DatabasePOD *db, IdString &wire);
DelayInfo getWireTypeDelay(IdString wire);
void read_cst(std::istream &in);
diff --git a/gowin/arch_pybindings.cc b/gowin/arch_pybindings.cc
index b968f55f..f0a0ed64 100644
--- a/gowin/arch_pybindings.cc
+++ b/gowin/arch_pybindings.cc
@@ -151,7 +151,6 @@ void arch_wrap_python(py::module &m)
fn_wrapper_2a_v<Context, decltype(&Context::addClock), &Context::addClock, conv_from_str<IdString>,
pass_through<float>>::def_wrap(ctx_cls, "addClock");
-
WRAP_MAP_UPTR(m, CellMap, "IdCellMap");
WRAP_MAP_UPTR(m, NetMap, "IdNetMap");
WRAP_MAP(m, HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
diff --git a/gowin/cells.cc b/gowin/cells.cc
index db7154a0..e45cd482 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -19,10 +19,10 @@
*/
#include "cells.h"
+#include <iostream>
#include "design_utils.h"
#include "log.h"
#include "util.h"
-#include <iostream>
NEXTPNR_NAMESPACE_BEGIN
diff --git a/gowin/main.cc b/gowin/main.cc
index c845821d..308be4d3 100644
--- a/gowin/main.cc
+++ b/gowin/main.cc
@@ -57,7 +57,7 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(std::unordered_map<s
std::regex devicere = std::regex("GW1N([A-Z]*)-(LV|UV)([0-9])([A-Z]{2}[0-9]+)(C[0-9]/I[0-9])");
std::smatch match;
std::string device = vm["device"].as<std::string>();
- if(!std::regex_match(device, match, devicere)) {
+ if (!std::regex_match(device, match, devicere)) {
log_error("Invalid device %s\n", device.c_str());
}
ArchArgs chipArgs;
diff --git a/gowin/pack.cc b/gowin/pack.cc
index ce96fd62..204f1c22 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -19,13 +19,13 @@
*/
#include <algorithm>
+#include <iostream>
#include <iterator>
#include <unordered_set>
#include "cells.h"
#include "design_utils.h"
#include "log.h"
#include "util.h"
-#include <iostream>
NEXTPNR_NAMESPACE_BEGIN
@@ -41,8 +41,7 @@ static void pack_lut_lutffs(Context *ctx)
if (ctx->verbose)
log_info("cell '%s' is of type '%s'\n", ctx->nameOf(ci), ci->type.c_str(ctx));
if (is_lut(ctx, ci)) {
- std::unique_ptr<CellInfo> packed =
- create_generic_cell(ctx, ctx->id("SLICE"), ci->name.str(ctx) + "_LC");
+ std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, ctx->id("SLICE"), ci->name.str(ctx) + "_LC");
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
packed_cells.insert(ci->name);
if (ctx->verbose)
@@ -96,8 +95,7 @@ static void pack_nonlut_ffs(Context *ctx)
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (is_ff(ctx, ci)) {
- std::unique_ptr<CellInfo> packed =
- create_generic_cell(ctx, ctx->id("SLICE"), ci->name.str(ctx) + "_DFFLC");
+ std::unique_ptr<CellInfo> packed = create_generic_cell(ctx, ctx->id("SLICE"), ci->name.str(ctx) + "_DFFLC");
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(packed->attrs, packed->attrs.begin()));
if (ctx->verbose)
log_info("packed cell %s into %s\n", ctx->nameOf(ci), ctx->nameOf(packed.get()));
@@ -196,9 +194,9 @@ static bool is_nextpnr_iob(const Context *ctx, CellInfo *cell)
cell->type == ctx->id("$nextpnr_iobuf");
}
-static bool is_gowin_iob(const Context *ctx, const CellInfo *cell) {
- switch (cell->type.index)
- {
+static bool is_gowin_iob(const Context *ctx, const CellInfo *cell)
+{
+ switch (cell->type.index) {
case ID_IBUF:
case ID_OBUF:
case ID_IOBUF:
@@ -207,7 +205,7 @@ static bool is_gowin_iob(const Context *ctx, const CellInfo *cell) {
default:
return false;
}
- }
+}
// Pack IO buffers
static void pack_io(Context *ctx)
@@ -222,8 +220,7 @@ static void pack_io(Context *ctx)
CellInfo *ci = cell.second;
if (is_gowin_iob(ctx, ci)) {
CellInfo *iob = nullptr;
- switch (ci->type.index)
- {
+ switch (ci->type.index) {
case ID_IBUF:
iob = net_driven_by(ctx, ci->ports.at(id_I).net, is_nextpnr_iob, id_O);
break;
@@ -247,8 +244,7 @@ static void pack_io(Context *ctx)
packed_cells.insert(iob->name);
}
// Create a IOB buffer
- std::unique_ptr<CellInfo> ice_cell =
- create_generic_cell(ctx, id_IOB, ci->name.str(ctx) + "$iob");
+ std::unique_ptr<CellInfo> ice_cell = create_generic_cell(ctx, id_IOB, ci->name.str(ctx) + "$iob");
gwio_to_iob(ctx, ci, ice_cell.get(), packed_cells);
new_cells.push_back(std::move(ice_cell));
auto gwiob = new_cells.back().get();
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-21 09:48:51 +0000