diff options
| -rw-r--r-- | machxo2/arch.cc | 5 | ||||
| -rw-r--r-- | machxo2/archdefs.h | 7 |
2 files changed, 4 insertions, 8 deletions
diff --git a/machxo2/arch.cc b/machxo2/arch.cc index df9b7efc..2938f1ba 100644 --- a/machxo2/arch.cc +++ b/machxo2/arch.cc @@ -401,7 +401,10 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const { ArcBounds bb; - + bb.x0 = std::min(src.location.x, dst.location.x); + bb.y0 = std::min(src.location.y, dst.location.y); + bb.x1 = std::max(src.location.x, dst.location.x); + bb.y1 = std::max(src.location.y, dst.location.y); return bb; } diff --git a/machxo2/archdefs.h b/machxo2/archdefs.h index caa15ece..844a87b6 100644 --- a/machxo2/archdefs.h +++ b/machxo2/archdefs.h @@ -129,13 +129,6 @@ struct NetInfo; struct ArchCellInfo { - // Custom grouping set via "PACK_GROUP" attribute. All cells with the same group - // value may share a tile (-1 = don't care, default if not set) - int user_group; - // Is a slice type primitive - bool is_slice; - // Only packing rule for slice type primitives is a single clock per tile - const NetInfo *slice_clk; }; NEXTPNR_NAMESPACE_END |