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| author | David Shah <dave@ds0.me> | 2019-04-04 16:30:47 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-04-04 16:34:06 +0100 |
| commit | f0cd51e6bc58f3dfd1185fd53ad970ba634359f2 (patch) | |
| tree | dd153f0b4cdd8ce2e62e22dbe0df1c37636956ee /generic/examples/README.md | |
| parent | 3f98084021b64420c36c171cc1245248d6968f03 (diff) | |
| download | nextpnr-f0cd51e6bc58f3dfd1185fd53ad970ba634359f2.tar.gz nextpnr-f0cd51e6bc58f3dfd1185fd53ad970ba634359f2.tar.bz2 nextpnr-f0cd51e6bc58f3dfd1185fd53ad970ba634359f2.zip | |
generic: Cell timing support
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'generic/examples/README.md')
| -rw-r--r-- | generic/examples/README.md | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/generic/examples/README.md b/generic/examples/README.md index 4641f542..dd154a51 100644 --- a/generic/examples/README.md +++ b/generic/examples/README.md @@ -4,6 +4,8 @@ This contains a simple, artificial, example of the nextpnr generic API. - simple.py procedurally generates a simple FPGA architecture with IO at the edges, logic slices in all other tiles, and interconnect only between adjacent tiles + + - simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing) - report.py stores design information after place-and-route to blinky.txt in place of real bitstream generation |