diff options
Diffstat (limited to 'ice40/regressions')
| -rw-r--r-- | ice40/regressions/issue0090/conn-crash.json | 5339 | ||||
| -rw-r--r-- | ice40/regressions/issue0090/conn-crash.npnr | 1 | ||||
| -rw-r--r-- | ice40/regressions/issue0090/conn-crash.pcf | 9 | ||||
| -rw-r--r-- | ice40/regressions/issue0090/conn-crash.sh | 3 | ||||
| -rw-r--r-- | ice40/regressions/issue0090/conn-crash.v | 43 | ||||
| -rw-r--r-- | ice40/regressions/issue0090/conn-crash.ys | 3 |
6 files changed, 5398 insertions, 0 deletions
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b/ice40/regressions/issue0090/conn-crash.npnr @@ -0,0 +1 @@ +--up5k --package sg48 --freq 12.000048000192 diff --git a/ice40/regressions/issue0090/conn-crash.pcf b/ice40/regressions/issue0090/conn-crash.pcf new file mode 100644 index 0000000..bd616a9 --- /dev/null +++ b/ice40/regressions/issue0090/conn-crash.pcf @@ -0,0 +1,9 @@ +set_io sevenseg_segment7 32 +set_io sevenseg_segment6 38 +set_io sevenseg_segment5 31 +set_io sevenseg_segment4 28 +set_io sevenseg_segment3 37 +set_io sevenseg_segment2 35 +set_io sevenseg_segment1 34 +set_io sevenseg_enable0 43 +set_io clk12 35 diff --git a/ice40/regressions/issue0090/conn-crash.sh b/ice40/regressions/issue0090/conn-crash.sh new file mode 100644 index 0000000..57a20ef --- /dev/null +++ b/ice40/regressions/issue0090/conn-crash.sh @@ -0,0 +1,3 @@ +:> conn-crash.log +${NPNR} --json conn-crash.json --asc conn-crash.asc --pcf conn-crash.pcf `cat conn-crash.npnr` > conn-crash.log 2>&1 || true +grep "^ERROR: Cell 'clk12\$sb_io' cannot be bound to bel 'X12/Y31/io1' since it is already bound to cell 'sevenseg_segment2\$sb_io'$" conn-crash.log diff --git a/ice40/regressions/issue0090/conn-crash.v b/ice40/regressions/issue0090/conn-crash.v new file mode 100644 index 0000000..5b58b5b --- /dev/null +++ b/ice40/regressions/issue0090/conn-crash.v @@ -0,0 +1,43 @@ +/* Machine-generated using Migen */ +module top( + output sevenseg_segment7, + output sevenseg_segment6, + output sevenseg_segment5, + output sevenseg_segment4, + output sevenseg_segment3, + output sevenseg_segment2, + output sevenseg_segment1, + output sevenseg_enable0, + input clk12 +); + +wire sys_clk; +wire sys_rst; +wire por_clk; +reg int_rst = 1'd1; + + +// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator +// to run the combinatorial process once at the beginning. +// synthesis translate_off +reg dummy_s; +initial dummy_s <= 1'd0; +// synthesis translate_on + +assign sevenseg_enable0 = 1'd1; +assign sevenseg_segment7 = 1'd1; +assign sevenseg_segment6 = 1'd1; +assign sevenseg_segment5 = 1'd1; +assign sevenseg_segment4 = 1'd1; +assign sevenseg_segment3 = 1'd1; +assign sevenseg_segment2 = 1'd1; +assign sevenseg_segment1 = 1'd1; +assign sys_clk = clk12; +assign por_clk = clk12; +assign sys_rst = int_rst; + +always @(posedge por_clk) begin + int_rst <= 1'd0; +end + +endmodule diff --git a/ice40/regressions/issue0090/conn-crash.ys b/ice40/regressions/issue0090/conn-crash.ys new file mode 100644 index 0000000..3318e30 --- /dev/null +++ b/ice40/regressions/issue0090/conn-crash.ys @@ -0,0 +1,3 @@ +read_verilog conn-crash.v +attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0 +synth_ice40 -top top -json conn-crash.json
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