From 9c9983cff8d5ff4c410b6f4fcd1c78b5f9e1fd6b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 4 Dec 2015 11:46:08 +0100 Subject: Added lutff_i/lout net to model --- icebox/icebox_vlog.py | 17 +++++++---------- icebox/iceboxdb.py | 14 +++++++------- 2 files changed, 14 insertions(+), 17 deletions(-) (limited to 'icebox') diff --git a/icebox/icebox_vlog.py b/icebox/icebox_vlog.py index b53cdfe..f88bb56 100755 --- a/icebox/icebox_vlog.py +++ b/icebox/icebox_vlog.py @@ -770,6 +770,7 @@ for lut in luts_queue: net_in2 = seg_to_net((lut[0], lut[1], "lutff_%d/in_2" % lut[2]), "1'b0") net_in3 = seg_to_net((lut[0], lut[1], "lutff_%d/in_3" % lut[2]), "1'b0") net_out = seg_to_net((lut[0], lut[1], "lutff_%d/out" % lut[2])) + net_lout = seg_to_net((lut[0], lut[1], "lutff_%d/lout" % lut[2])) if seq_bits[0] == "1": net_cout = seg_to_net((lut[0], lut[1], "lutff_%d/cout" % lut[2])) net_in1 = seg_to_net((lut[0], lut[1], "lutff_%d/in_1" % lut[2]), "1'b0") @@ -787,24 +788,20 @@ for lut in luts_queue: carry_assigns.append([net_cout, "/* CARRY %2d %2d %2d */ (%s & %s) | ((%s | %s) & %s)" % (lut[0], lut[1], lut[2], net_in1, net_in2, net_in1, net_in2, net_cin)]) if seq_bits[1] == "1": - n = next_netname() - text_wires.append("wire %s;" % n) - if not strip_comments: - text_wires.append("// FF %s" % (lut,)) - text_wires.append("") net_cen = seg_to_net((lut[0], lut[1], "lutff_global/cen"), "1'b1") net_clk = seg_to_net((lut[0], lut[1], "lutff_global/clk"), "1'b0") net_sr = seg_to_net((lut[0], lut[1], "lutff_global/s_r"), "1'b0") if seq_bits[3] == "0": always_stmts.append("/* FF %2d %2d %2d */ always @(%sedge %s) if (%s) %s <= %s ? 1'b%s : %s;" % (lut[0], lut[1], lut[2], "neg" if icebox.get_negclk_bit(tile) == "1" else "pos", - net_clk, net_cen, net_out, net_sr, seq_bits[2], n)) + net_clk, net_cen, net_out, net_sr, seq_bits[2], net_lout)) else: always_stmts.append("/* FF %2d %2d %2d */ always @(%sedge %s, posedge %s) if (%s) %s <= 1'b%s; else if (%s) %s <= %s;" % (lut[0], lut[1], lut[2], "neg" if icebox.get_negclk_bit(tile) == "1" else "pos", - net_clk, net_sr, net_sr, net_out, seq_bits[2], net_cen, net_out, n)) + net_clk, net_sr, net_sr, net_out, seq_bits[2], net_cen, net_out, net_lout)) wire_to_reg.add(net_out.strip()) - net_out = n + else: + always_stmts.append("/* FF %2d %2d %2d */ assign %s = %s;" % (lut[0], lut[1], lut[2], net_out, net_lout)) if not "1" in lut_bits: const_assigns.append([net_out, "1'b0"]) elif not "0" in lut_bits: @@ -822,8 +819,8 @@ for lut in luts_queue: if h_expr == "0" and l_expr == "1": return "!" + sigs[0] return "%s ? %s : %s" % (sigs[0], h_expr, l_expr) lut_expr = make_lut_expr(lut_bits, [net_in3, net_in2, net_in1, net_in0]) - lut_assigns.append([net_out, "/* LUT %2d %2d %2d */ %s" % (lut[0], lut[1], lut[2], lut_expr)]) - max_net_len = max(max_net_len, len(net_out)) + lut_assigns.append([net_lout, "/* LUT %2d %2d %2d */ %s" % (lut[0], lut[1], lut[2], lut_expr)]) + max_net_len = max(max_net_len, len(net_lout)) for a in const_assigns + lut_assigns + carry_assigns: text_func.append("assign %-*s = %s;" % (max_net_len, a[0], a[1])) diff --git a/icebox/iceboxdb.py b/icebox/iceboxdb.py index 8f07dbc..dbbe765 100644 --- a/icebox/iceboxdb.py +++ b/icebox/iceboxdb.py @@ -1960,7 +1960,7 @@ B6[15],!B6[16],B6[17],!B6[18],B7[18] buffer top_op_5 lc_trk_g1_5 !B6[21],B6[22],!B6[23],B6[24],B7[21] buffer top_op_7 lc_trk_g1_7 !B0[31],B0[32],!B0[33],!B0[34],!B1[31] buffer wire_logic_cluster/carry_in_mux/cout wire_logic_cluster/lc_0/in_3 !B2[31],B2[32],!B2[33],!B2[34],!B3[31] buffer wire_logic_cluster/lc_0/cout wire_logic_cluster/lc_1/in_3 -B2[50] buffer wire_logic_cluster/lc_0/out input_2_1 +B2[50] buffer wire_logic_cluster/lc_0/lout input_2_1 B0[14],!B1[14],!B1[15],!B1[16],B1[17] buffer wire_logic_cluster/lc_0/out lc_trk_g0_0 B4[14],!B5[14],!B5[15],!B5[16],B5[17] buffer wire_logic_cluster/lc_0/out lc_trk_g1_0 B8[14],!B9[14],!B9[15],!B9[16],B9[17] buffer wire_logic_cluster/lc_0/out lc_trk_g2_0 @@ -1978,7 +1978,7 @@ B0[48] buffer wire_logic_cluster/lc_0/out sp4_v_b_0 B1[51] buffer wire_logic_cluster/lc_0/out sp4_v_t_21 B1[48] buffer wire_logic_cluster/lc_0/out sp4_v_t_5 !B4[31],B4[32],!B4[33],!B4[34],!B5[31] buffer wire_logic_cluster/lc_1/cout wire_logic_cluster/lc_2/in_3 -B4[50] buffer wire_logic_cluster/lc_1/out input_2_2 +B4[50] buffer wire_logic_cluster/lc_1/lout input_2_2 !B0[15],!B0[16],B0[17],B0[18],!B1[18] buffer wire_logic_cluster/lc_1/out lc_trk_g0_1 !B4[15],!B4[16],B4[17],B4[18],!B5[18] buffer wire_logic_cluster/lc_1/out lc_trk_g1_1 !B8[15],!B8[16],B8[17],B8[18],!B9[18] buffer wire_logic_cluster/lc_1/out lc_trk_g2_1 @@ -1996,7 +1996,7 @@ B3[48] buffer wire_logic_cluster/lc_1/out sp4_v_b_18 B2[48] buffer wire_logic_cluster/lc_1/out sp4_v_b_2 B3[51] buffer wire_logic_cluster/lc_1/out sp4_v_t_23 !B6[31],B6[32],!B6[33],!B6[34],!B7[31] buffer wire_logic_cluster/lc_2/cout wire_logic_cluster/lc_3/in_3 -B6[50] buffer wire_logic_cluster/lc_2/out input_2_3 +B6[50] buffer wire_logic_cluster/lc_2/lout input_2_3 B0[25],B1[22],!B1[23],!B1[24],!B1[25] buffer wire_logic_cluster/lc_2/out lc_trk_g0_2 B4[25],B5[22],!B5[23],!B5[24],!B5[25] buffer wire_logic_cluster/lc_2/out lc_trk_g1_2 B8[25],B9[22],!B9[23],!B9[24],!B9[25] buffer wire_logic_cluster/lc_2/out lc_trk_g2_2 @@ -2014,7 +2014,7 @@ B5[51] buffer wire_logic_cluster/lc_2/out sp4_v_b_36 B4[48] buffer wire_logic_cluster/lc_2/out sp4_v_b_4 B5[48] buffer wire_logic_cluster/lc_2/out sp4_v_t_9 !B8[31],B8[32],!B8[33],!B8[34],!B9[31] buffer wire_logic_cluster/lc_3/cout wire_logic_cluster/lc_4/in_3 -B8[50] buffer wire_logic_cluster/lc_3/out input_2_4 +B8[50] buffer wire_logic_cluster/lc_3/lout input_2_4 B0[21],B0[22],!B0[23],!B0[24],!B1[21] buffer wire_logic_cluster/lc_3/out lc_trk_g0_3 B4[21],B4[22],!B4[23],!B4[24],!B5[21] buffer wire_logic_cluster/lc_3/out lc_trk_g1_3 B8[21],B8[22],!B8[23],!B8[24],!B9[21] buffer wire_logic_cluster/lc_3/out lc_trk_g2_3 @@ -2032,7 +2032,7 @@ B7[48] buffer wire_logic_cluster/lc_3/out sp4_v_b_22 B7[51] buffer wire_logic_cluster/lc_3/out sp4_v_b_38 B6[48] buffer wire_logic_cluster/lc_3/out sp4_v_b_6 !B10[31],B10[32],!B10[33],!B10[34],!B11[31] buffer wire_logic_cluster/lc_4/cout wire_logic_cluster/lc_5/in_3 -B10[50] buffer wire_logic_cluster/lc_4/out input_2_5 +B10[50] buffer wire_logic_cluster/lc_4/lout input_2_5 B2[14],!B3[14],!B3[15],!B3[16],B3[17] buffer wire_logic_cluster/lc_4/out lc_trk_g0_4 B6[14],!B7[14],!B7[15],!B7[16],B7[17] buffer wire_logic_cluster/lc_4/out lc_trk_g1_4 B10[14],!B11[14],!B11[15],!B11[16],B11[17] buffer wire_logic_cluster/lc_4/out lc_trk_g2_4 @@ -2050,7 +2050,7 @@ B9[51] buffer wire_logic_cluster/lc_4/out sp4_v_b_24 B9[48] buffer wire_logic_cluster/lc_4/out sp4_v_b_8 B8[51] buffer wire_logic_cluster/lc_4/out sp4_v_t_29 !B12[31],B12[32],!B12[33],!B12[34],!B13[31] buffer wire_logic_cluster/lc_5/cout wire_logic_cluster/lc_6/in_3 -B12[50] buffer wire_logic_cluster/lc_5/out input_2_6 +B12[50] buffer wire_logic_cluster/lc_5/lout input_2_6 !B2[15],!B2[16],B2[17],B2[18],!B3[18] buffer wire_logic_cluster/lc_5/out lc_trk_g0_5 !B6[15],!B6[16],B6[17],B6[18],!B7[18] buffer wire_logic_cluster/lc_5/out lc_trk_g1_5 !B10[15],!B10[16],B10[17],B10[18],!B11[18] buffer wire_logic_cluster/lc_5/out lc_trk_g2_5 @@ -2068,7 +2068,7 @@ B11[48] buffer wire_logic_cluster/lc_5/out sp4_v_b_10 B11[51] buffer wire_logic_cluster/lc_5/out sp4_v_b_26 B10[51] buffer wire_logic_cluster/lc_5/out sp4_v_b_42 !B14[31],B14[32],!B14[33],!B14[34],!B15[31] buffer wire_logic_cluster/lc_6/cout wire_logic_cluster/lc_7/in_3 -B14[50] buffer wire_logic_cluster/lc_6/out input_2_7 +B14[50] buffer wire_logic_cluster/lc_6/lout input_2_7 B2[25],B3[22],!B3[23],!B3[24],!B3[25] buffer wire_logic_cluster/lc_6/out lc_trk_g0_6 B6[25],B7[22],!B7[23],!B7[24],!B7[25] buffer wire_logic_cluster/lc_6/out lc_trk_g1_6 B10[25],B11[22],!B11[23],!B11[24],!B11[25] buffer wire_logic_cluster/lc_6/out lc_trk_g2_6 -- cgit v1.2.3