From 9c9983cff8d5ff4c410b6f4fcd1c78b5f9e1fd6b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 4 Dec 2015 11:46:08 +0100 Subject: Added lutff_i/lout net to model --- docs/logic_tile.html | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'docs/logic_tile.html') diff --git a/docs/logic_tile.html b/docs/logic_tile.html index 67524bb..982b25d 100644 --- a/docs/logic_tile.html +++ b/docs/logic_tile.html @@ -228,8 +228,10 @@ or asynchronous exist for each logic cell individually. Each LUT i has four input wires lutff_i/in_0 to lutff_i/in_3. Input lutff_i/in_3 can be configured to be driven by the carry output of the previous logic cell, or by carry_in_mux in case of i=0. Input lutff_i/in_2 can be configured to -be driven by the output of the previous LUT for i>0. The LUT uses its 4 input signals to -calculate lutff_i/out. +be driven by the output of the previous LUT for i>0 (LUT cascade). The LUT uses its 4 input signals to +calculate lutff_i/lout. The signal is then passed through the built-in FF +and becomes lutff_i/out. With the exception of LUT cascades, only the signal +after the FF is visible from outside the logic block.

@@ -294,7 +296,7 @@ The LUT implements the following truth table:

- + -- cgit v1.2.3
in_3in_2in_1in_0out
in_3in_2in_1in_0lout
0000LC_i[4]
0001LC_i[14]
0010LC_i[15]