From bb519401cd4facc45cfc491a583b8d4eb823f00b Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Wed, 1 Feb 2023 10:22:27 +0100
Subject: icebox: Add PLL ICEGATE function

Only tested on UP5k. For others, it was just deduced.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 docs/io_tile.html | 11 +++++++++++
 icebox/icebox.py  | 12 ++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/docs/io_tile.html b/docs/io_tile.html
index 82cf65b..2b074ca 100644
--- a/docs/io_tile.html
+++ b/docs/io_tile.html
@@ -428,6 +428,9 @@ follows (bits listed from LSB to MSB):
 
 <tr><td>0 3</td><td><span style="font-family:monospace">PLLCONFIG_8</span></td><td rowspan="1"><span style="font-family:monospace">TEST_MODE</span></td></tr>
 
+<tr><td>0 5</td><td><span style="font-family:monospace">PLLCONFIG_2</span></td><td rowspan="1">Enable ICEGATE for <span style="font-family:monospace">PLLOUTGLOBALA</span></td></tr>
+<tr><td>0 5</td><td><span style="font-family:monospace">PLLCONFIG_4</span></td><td rowspan="1">Enable ICEGATE for <span style="font-family:monospace">PLLOUTGLOBALB</span></td></tr>
+
 </table></td><td>
 
 <table class="ctab">
@@ -502,4 +505,12 @@ PIOs can only be used as output Pins by the FPGA fabric when the PLL ports
 are being used.
 </p>
 
+<p>
+The input path that are stolen are also used to implement the ICEGATE function.
+If the input pin type of the input path being stolen is set to
+<span style="font-family:monospace">PIN_INPUT_LATCH</span>, then the ICEGATE
+function is enabled for the corresponding <span style="font-family:monospace">CORE</span>
+output of the PLL.
+</p>
+
 </body></html>
diff --git a/icebox/icebox.py b/icebox/icebox.py
index ef5478b..a1c0c09 100644
--- a/icebox/icebox.py
+++ b/icebox/icebox.py
@@ -1795,6 +1795,8 @@ pllinfo_db = {
         "FILTER_RANGE_1":       ( 0,  2, "PLLCONFIG_7"),
         "FILTER_RANGE_2":       ( 0,  2, "PLLCONFIG_8"),
         "TEST_MODE":            ( 0,  3, "PLLCONFIG_8"),
+        "ENABLE_ICEGATE_PORTA": ( 0,  5, "PLLCONFIG_2"), # Controls global output only !
+        "ENABLE_ICEGATE_PORTB": ( 0,  5, "PLLCONFIG_4"), # Controls global output only !
 
         # PLL Ports
         "PLLOUT_A":             ( 6,  0, 1),
@@ -1887,6 +1889,8 @@ pllinfo_db = {
         "FILTER_RANGE_1":       (11,  0, "PLLCONFIG_7"),
         "FILTER_RANGE_2":       (11,  0, "PLLCONFIG_8"),
         "TEST_MODE":            (12,  0, "PLLCONFIG_8"),
+        "ENABLE_ICEGATE_PORTA": (14,  0, "PLLCONFIG_2"), # Controls global output only !
+        "ENABLE_ICEGATE_PORTB": (14,  0, "PLLCONFIG_4"), # Controls global output only !
 
         # PLL Ports
         # TODO(awygle) confirm these
@@ -1981,6 +1985,8 @@ pllinfo_db = {
         "FILTER_RANGE_1":       (11, 31, "PLLCONFIG_7"),
         "FILTER_RANGE_2":       (11, 31, "PLLCONFIG_8"),
         "TEST_MODE":            (12, 31, "PLLCONFIG_8"),
+        "ENABLE_ICEGATE_PORTA": (14, 31, "PLLCONFIG_2"), # Controls global output only !
+        "ENABLE_ICEGATE_PORTB": (14, 31, "PLLCONFIG_4"), # Controls global output only !
 
         # PLL Ports
         "PLLOUT_A":             ( 12, 31, 1), 
@@ -2045,6 +2051,8 @@ pllinfo_db = {
         "TEST_MODE":            (12, 21, "PLLCONFIG_8"),
         "DELAY_ADJMODE_FB":     (13, 21, "PLLCONFIG_4"),
         "DELAY_ADJMODE_REL":    (13, 21, "PLLCONFIG_9"),
+        "ENABLE_ICEGATE_PORTA": (14, 21, "PLLCONFIG_2"), # Controls global output only !
+        "ENABLE_ICEGATE_PORTB": (14, 21, "PLLCONFIG_4"), # Controls global output only !
 
         # PLL Ports
         "PLLOUT_A":             ( 12, 21, 1),
@@ -2138,6 +2146,8 @@ pllinfo_db = {
         "FILTER_RANGE_1":       ( 15, 0, "PLLCONFIG_7"),
         "FILTER_RANGE_2":       ( 15, 0, "PLLCONFIG_8"),
         "TEST_MODE":            ( 16, 0, "PLLCONFIG_8"),
+        "ENABLE_ICEGATE_PORTA": ( 18, 0, "PLLCONFIG_2"), # Controls global output only !
+        "ENABLE_ICEGATE_PORTB": ( 18, 0, "PLLCONFIG_4"), # Controls global output only !
 
         # PLL Ports
         "PLLOUT_A":             ( 16, 0, 1),
@@ -2231,6 +2241,8 @@ pllinfo_db = {
         "FILTER_RANGE_1":       ( 15, 33, "PLLCONFIG_7"),
         "FILTER_RANGE_2":       ( 15, 33, "PLLCONFIG_8"),
         "TEST_MODE":            ( 16, 33, "PLLCONFIG_8"),
+        "ENABLE_ICEGATE_PORTA": ( 18, 33, "PLLCONFIG_2"), # Controls global output only !
+        "ENABLE_ICEGATE_PORTB": ( 18, 33, "PLLCONFIG_4"), # Controls global output only !
 
         # PLL Ports
         "PLLOUT_A":             ( 16, 33, 1),
-- 
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