From d8d30fa63000fab66e770db996c4bb90dcb90420 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 12 Jun 2018 19:10:15 -0700 Subject: icebox_hlc2asc: Remove the bidirectional support. See ca6b2d9ebd521ecec58b9b5627c9380355adeab1. --- icebox/icebox_hlc2asc.py | 8 -------- 1 file changed, 8 deletions(-) diff --git a/icebox/icebox_hlc2asc.py b/icebox/icebox_hlc2asc.py index 54c9dc0..3b9ee38 100755 --- a/icebox/icebox_hlc2asc.py +++ b/icebox/icebox_hlc2asc.py @@ -701,14 +701,6 @@ class Tile: continue add_entry(entry, bits) - # Let the routing bits be specified in both a->b and b->a direction. - for bits, *entry in self.db: - if not ic.tile_has_entry(x, y, (bits, *entry)): - continue - if entry[0] != "routing": - continue - add_entry((entry[0], entry[2], entry[1]), bits) - self.buffers = [] self.routings = [] self.bits_set = set() -- cgit v1.2.3 From 82f2f3d278fe64a8053cb633e98287b21bb4b684 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 12 Jun 2018 19:15:17 -0700 Subject: HLC: Use '~>' instead of '<->' for routing switches. As mentioned in ca6b2d9ebd521ecec58b9b5627c9380355adeab1, the 'routing' switches are not actually bidirectional. This makes the '<->' specifier very misleading. Instead use '~>' to differentiate it from the 'buffer' switches. --- icebox/icebox_asc2hlc.py | 2 +- icebox/icebox_hlc2asc.py | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/icebox/icebox_asc2hlc.py b/icebox/icebox_asc2hlc.py index 4f0f6fa..facca4b 100755 --- a/icebox/icebox_asc2hlc.py +++ b/icebox/icebox_asc2hlc.py @@ -797,7 +797,7 @@ class Tile: self.ic.max_y - 1, entry[3]) if dst == 'fabout': dst = lookup_fabout(*self.xy) - self.buffer_and_routing.add((src, '<->', dst)) + self.buffer_and_routing.add((src, '~>', dst)) continue if entry[1] == 'buffer': if match: diff --git a/icebox/icebox_hlc2asc.py b/icebox/icebox_hlc2asc.py index 3b9ee38..00ed050 100755 --- a/icebox/icebox_hlc2asc.py +++ b/icebox/icebox_hlc2asc.py @@ -775,7 +775,7 @@ clearing:{:<30} - current set :{}""".format( if (src, dst) not in self.buffers: self.buffers.append((src, dst)) self.apply_directive('buffer', src, dst) - elif len(fields) == 3 and fields[1] == '<->': + elif len(fields) == 3 and fields[1] == '~>': src = untranslate_netname(self.x, self.y, self.ic.max_x - 1, self.ic.max_y - 1, fields[0]) @@ -786,7 +786,7 @@ clearing:{:<30} - current set :{}""".format( if (src, dst) not in self.routings: self.routings.append((src, dst)) self.apply_directive('routing', src, dst) - elif len(fields) >= 5 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) >= 5 and (fields[1] == '->' or fields[1] == '~>'): self.read(fields[:3]) self.read(fields[2:]) else: @@ -840,11 +840,11 @@ class LogicCell: self.seq_bits[2] = '1' elif fields == ['async_setreset']: self.seq_bits[3] = '1' - elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '~>'): self.read(fields[:3]) self.read(fields[2:]) return - elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '~>'): prefix = 'lutff_%d/' % self.index # Strip prefix if it is given @@ -1001,10 +1001,10 @@ class IOBlock: == ("padin_glb_netwk", fields[2][10:])] assert len(bit) == 1 self.tile.ic.extra_bits.add(bit[0]) - elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) > 3 and (fields[1] == '->' or fields[1] == '~>'): self.read(fields[:3]) self.read(fields[2:]) - elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '<->'): + elif len(fields) == 3 and (fields[1] == '->' or fields[1] == '~>'): prefix = 'io_%d/' % self.index # Strip prefix if it is given -- cgit v1.2.3