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-rw-r--r--icefuzz/tests/colbufs.v43
1 files changed, 34 insertions, 9 deletions
diff --git a/icefuzz/tests/colbufs.v b/icefuzz/tests/colbufs.v
index b84c189..fe086a9 100644
--- a/icefuzz/tests/colbufs.v
+++ b/icefuzz/tests/colbufs.v
@@ -1,18 +1,17 @@
module top #(
- parameter NUM_BITS = 8
+ parameter NUM_BITS = 1
) (
input [NUM_BITS-1:0] clk,
- output reg [NUM_BITS-1:0] y
+ output [NUM_BITS-1:0] y
);
- wire [NUM_BITS-1:0] t1;
- reg [NUM_BITS-1:0] t2;
+ wire [NUM_BITS-1:0] t1, t2, t3;
genvar i;
generate for (i = 0; i < NUM_BITS; i = i+1) begin:bitslice
SB_RAM40_4K #(
.READ_MODE(0),
.WRITE_MODE(0)
- ) ram40 (
+ ) ram40_upper (
.WADDR(8'b0),
.RADDR(8'b0),
.MASK(~16'b0),
@@ -26,9 +25,35 @@ module top #(
.RCLK(clk[i])
);
- always @(posedge clk[i]) begin
- t2[i] <= t1[i];
- y[i] <= t2[i];
- end
+ SB_RAM40_4K #(
+ .READ_MODE(0),
+ .WRITE_MODE(0)
+ ) ram40_lower (
+ .WADDR(8'b0),
+ .RADDR(8'b0),
+ .MASK(~16'b0),
+ .WDATA(8'b0),
+ .RDATA(t2[i]),
+ .WE(1'b1),
+ .WCLKE(1'b1),
+ .WCLK(clk[i]),
+ .RE(1'b1),
+ .RCLKE(1'b1),
+ .RCLK(clk[i])
+ );
+
+ SB_DFF dff (
+ .C(clk[i]),
+ .D(t1[i] ^ t2[i]),
+ .Q(t3[i])
+ );
+
+ SB_IO #(
+ .PIN_TYPE(6'b 0101_01)
+ ) out (
+ .PACKAGE_PIN(y[i]),
+ .OUTPUT_CLK(clk[i]),
+ .D_OUT_0(t3[i])
+ );
end endgenerate
endmodule