diff options
Diffstat (limited to 'icebox/icebox_hlc2asc.py')
| -rwxr-xr-x | icebox/icebox_hlc2asc.py | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/icebox/icebox_hlc2asc.py b/icebox/icebox_hlc2asc.py index f10a0e9..08b5556 100755 --- a/icebox/icebox_hlc2asc.py +++ b/icebox/icebox_hlc2asc.py @@ -832,8 +832,19 @@ class LogicCell: if fields[0] == 'lut' and len(fields) == 2 and self.lut_bits is None: self.lut_bits = fields[1] elif fields[0] == 'out' and len(fields) >= 3 and fields[1] == '=': - self.lut_bits = logic_expression_to_lut( - ' '.join(fields[2:]), ('in_0', 'in_1', 'in_2', 'in_3')) + m = re.match("([0-9]+)'b([01]+)", fields[2]) + if m: + lut_bits = m.group(2) + if len(lut_bits) != int(m.group(1)): + raise ParseError + m = len(lut_bits) + if m < 16: + lut_bits = (16-m) * "0" + lut_bits + # Verilog 16'bXXXX is MSB first but the bitstream wants LSB. + self.lut_bits = lut_bits[::-1] + else: + self.lut_bits = logic_expression_to_lut( + ' '.join(fields[2:]), ('in_0', 'in_1', 'in_2', 'in_3')) elif fields == ['enable_carry']: self.seq_bits[0] = '1' elif fields == ['enable_dff']: |