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-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
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-- ---------------------------------------------------------------------
--
-- $Id: test185.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
    FUNCTION  SIN (X : real ) RETURN real;
    FUNCTION  EXP  (X : real ) RETURN real;
END PACKAGE electricalSystem;

USE work.electricalSystem.all;

ENTITY simcase IS
END simcase;

ARCHITECTURE asimcase OF simcase IS

    terminal T1: electrical;

    quantity v1 across i1 through T1 ;

BEGIN  
	eq1: v1==1.0;
	if (v1<=1.0) use	
		e1: null;
	end use;
END asimcase ;