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-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

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-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-- ---------------------------------------------------------------------
--
-- $Id: test148.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of cincinnati
-- Cincinnati
----------------------------------------------------------------------
-- File          : test148.ams
-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created       : Sept 2001
-- Last modified :
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- the test checks for the correctness of the quantity, terminal, nature 
-- and package declarations. the terminals are assigned as terminals.
-- a simple V-R circuit is considered.
-----------------------------------------------------------------------

PACKAGE electricalsystem IS
    FUNCTION SIN(X : real) RETURN real;
    FUNCTION EXP(X : real) RETURN real;
    FUNCTION SQRT(X : real) RETURN real;
    FUNCTION POW(X,Y : real) RETURN real;

NATURE electrical IS real ACROSS real THROUGH ; --ground reference;

END PACKAGE electricalsystem;
use work.electricalsystem.all;

ENTITY test IS
    PORT (TERMINAL p: electrical);
END ENTITY test;

architecture atest of test is
quantity vr across ir through p;
begin
e2:    vr== ir*10.0;
end architecture atest;

use work.electricalsystem.all;

entity res is
end res;

ARCHITECTURE ares OF res IS
	component test is
	  port(terminal p:electrical);
	end component;
	for all : test use entity work.test(atest);
	terminal x:electrical;
	constant freq: real:=10000.0;
        quantity v across i through x;
BEGIN
r1:    test port map(p => x);
e1:    v == 5.0 * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12);
END ARCHITECTURE ares;