-- Copyright (C) 2001-2002 The University of Cincinnati.  
-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
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-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
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-- ---------------------------------------------------------------------
--
-- $Id: test113.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
----------------------------------------------------------------------
-- File          : test113.ams
-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created       : May 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- the test checks the correctness of the Q'Tolerance for across qnty
-- and for the real quantity.The test checks for the simpel diode 
-- implementation wherein the charge is evaluated wrt a relative 
-- tolerance value
-- the test doesn't seem to take a tolerance associated with a
-- free quantity. we need to check on this!! (LRM : 4.3.1 spec 
-- followed.
----------------------------------------------------------------

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH ground reference;
    FUNCTION SIN(X : real) RETURN real;
    FUNCTION EXP(X : real) RETURN real;
    FUNCTION SQRT(X : real) RETURN real;
    FUNCTION POW(X,Y : real) RETURN real;
END PACKAGE electricalSystem;
use work.electricalSystem.all;

entity test is
generic(a:real:=1.0e-10; b:real:=0.0);
port (terminal t1: electrical);

end entity;

architecture atest of test is
quantity vd across id through t1; -- to electrical'reference;
quantity charge:real tolerance "reltol=1.0e-2";
--quantity ic : real;
constant rd: real:=1.0;
begin
e1:     id== a*(sin((vd-id*rd)/0.5)-1.0);
e2:     charge== b*id; 
--e3:     ic==charge'dot;
end architecture;