-- Copyright (C) 2001-2002 The University of Cincinnati.  
-- All rights reserved. 

-- This file is part of VESTs (Vhdl tESTs).

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-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.

-- You should have received a copy of the GNU General Public License
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-- ---------------------------------------------------------------------
--
-- $Id: test103.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------

----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of cincinnati
-- Cincinnati
----------------------------------------------------------------------
-- File          : test103.ams
-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created       : May 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- the test checks the correctness of the simple simultaneous eqn.
-- implementation. This is also a test for the lexical analysis.
--------------------------------------------------------------------

PACKAGE electricalSystem IS
    NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE;
    FUNCTION SIN(X : real) RETURN real;
    FUNCTION EXP(X : real) RETURN real;
    FUNCTION SQRT(X : real) RETURN real;
    FUNCTION POW(X,Y : real) RETURN real;

END PACKAGE electricalSystem;
use work.electricalSystem.all;

entity test is
end entity;

architecture atest of test is
terminal T1,T2,T3,T4,T5:electrical;
quantity v1 across i1 through T1 to T2;
quantity v2 across i2 through T2 to T4;
quantity v3 across i3 through T4 to T3;
quantity v4 across i4 through T2 to T5;
quantity v5 across i5 through T5 to T3;
quantity v6 across i6 through T2 to T3;
quantity vS across T1 to electrical'reference;

begin

e1:	v1==i1*1.0;
e2:	v2==i2*1.0;
e3:	v3==i3*1.0;
e4:	v4==i4*1.0;
e5:	v5==i5*1.0;
e6: 	v6==i6*1.0;
es:	vS==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);

end architecture;