-- Common types. -- Copyright (C) 2002 - 2015 Tristan Gingold -- -- GHDL is free software; you can redistribute it and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation; either version 2, or (at your option) any later -- version. -- -- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY -- WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- -- You should have received a copy of the GNU General Public License -- along with GHDL; see the file COPYING. If not, write to the Free -- Software Foundation, 59 Temple Place - Suite 330, Boston, MA -- 02111-1307, USA. with Interfaces; package Types is pragma Preelaborate (Types); -- A tri state type. type Tri_State_Type is (Unknown, False, True); -- 32 bits integer. type Int32 is range -2**31 .. 2**31 - 1; for Int32'Size use 32; subtype Nat32 is Int32 range 0 .. Int32'Last; subtype Pos32 is Nat32 range 1 .. Nat32'Last; subtype Nat8 is Nat32 range 0 .. 255; type Uns32 is new Interfaces.Unsigned_32; type Fp64 is new Interfaces.IEEE_Float_64; -- iir_int32 is aimed at containing integer literal values. type Iir_Int32 is new Interfaces.Integer_32; -- iir_int64 is aimed at containing units values. type Iir_Int64 is new Interfaces.Integer_64; -- iir_fp64 is aimed at containing floating point values. subtype Iir_Fp64 is Fp64; -- iir_index32 is aimed at containing an array index. type Iir_Index32 is new Nat32; -- Useful types. type String_Acc is access String; type String_Cst is access constant String; type String_Acc_Array is array (Natural range <>) of String_Acc; -- The name table is defined in Name_Table package. This is an hash table -- that associate a uniq Name_Id to a string. Name_Id are allocated in -- increasing numbers, so it is possible to create a parallel table -- indexed on Name_Id to associate additional data to the names. type Name_Id is new Nat32; -- Null entry in the name table. -- It is sure that this entry is never allocated. Null_Identifier: constant Name_Id := 0; -- A String8_Id represents a string stored in a dedicated table. Contrary -- to Name_Id, String8 aren't uniq: two different String8_Id can correspond -- to a same String. The purpose of an integer number for string is to -- have a 32 bit type to represent a string (contrary to pointers that -- could be 32 or 64 bit - in general - or to an access type which can be -- even wider in Ada). type String8_Id is new Nat32; for String8_Id'Size use 32; Null_String8 : constant String8_Id := 0; -- Index type is the source file table. -- This table is defined in the files_map package. type Source_File_Entry is new Nat32; No_Source_File_Entry: constant Source_File_Entry := 0; -- FIXME: additional source file entries to create: -- *std.standard*: for those created in std.standard -- *error*: for erroneous one -- *command-line*: used for identifiers from command line -- (eg: unit to elab) -- Index into a file buffer. type Source_Ptr is new Int32; -- Lower boundary of any file buffer. Source_Ptr_Org : constant Source_Ptr := 0; -- Bad file buffer index (used to mark no line). Source_Ptr_Bad : constant Source_Ptr := -1; -- This type contains everything necessary to get a file name, a line -- number and a column number. type Location_Type is new Nat32; for Location_Type'Size use 32; Location_Nil : constant Location_Type := 0; No_Location : constant Location_Type := 0; -- Type of a file buffer. type File_Buffer is array (Source_Ptr range <>) of Character; type File_Buffer_Acc is access File_Buffer; -- PSL Node. type PSL_Node is new Int32; -- PSL NFA type PSL_NFA is new Int32; -- Indentation. -- This is used by all packages that display vhdl code or informations. Indentation : constant := 2; -- String representing a date/time (format is YYYYMMDDHHmmSS.sss). subtype Time_Stamp_String is String (1 .. 18); type Time_Stamp_Id is new String8_Id; Null_Time_Stamp : constant Time_Stamp_Id := 0; -- In order to detect file changes, a checksum of the content is computed. -- Currently SHA1 is used, but the cryptographic aspect is not a strong -- requirement. type File_Checksum_Id is new String8_Id; No_File_Checksum_Id : constant File_Checksum_Id := 0; -- String image of a File_Hash_Id. SHA1 digests are 5 * 32 bytes long, so -- the hexadecimal image is 40 characters. subtype File_Checksum_String is String (1 .. 40); -- Self-explaining: raised when an internal error (such as consistency) -- is detected. Internal_Error: exception; -- In some case, a low level subprogram can't handle error -- (e.g eval_pos). In this case it is easier to raise an exception and -- let upper level subprograms handle the case. Node_Error : exception; -- Result of a comparaison of two numeric values. type Order_Type is (Less, Equal, Greater); end Types; id='n73' href='#n73'>73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 
/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/yosys.h"
#include "kernel/sigtools.h"

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

void aiger_encode(std::ostream &f, int x)
{
	log_assert(x >= 0);

	while (x & ~0x7f) {
		f.put((x & 0x7f) | 0x80);
		x = x >> 7;
	}

	f.put(x);
}

struct AigerWriter
{
	Module *module;
	bool zinit_mode;
	SigMap sigmap;

	dict<SigBit, bool> init_map;
	pool<SigBit> input_bits, output_bits;
	dict<SigBit, SigBit> not_map, ff_map, alias_map;
	dict<SigBit, pair<SigBit, SigBit>> and_map;
	vector<pair<SigBit, SigBit>> asserts, assumes;
	vector<pair<SigBit, SigBit>> liveness, fairness;
	pool<SigBit> initstate_bits;

	vector<pair<int, int>> aig_gates;
	vector<int> aig_latchin, aig_latchinit, aig_outputs;
	int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
	int aig_b = 0, aig_c = 0, aig_j = 0, aig_f = 0;

	dict<SigBit, int> aig_map;
	dict<SigBit, int> ordered_outputs;
	dict<SigBit, int> ordered_latches;

	dict<SigBit, int> init_inputs;
	int initstate_ff = 0;

	int mkgate(int a0, int a1)
	{
		aig_m++, aig_a++;
		aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
		return 2*aig_m;
	}

	int bit2aig(SigBit bit)
	{
		auto it = aig_map.find(bit);
		if (it != aig_map.end()) {
			log_assert(it->second >= 0);
			return it->second;
		}

		// NB: Cannot use iterator returned from aig_map.insert()
		//     since this function is called recursively

		int a = -1;
		if (not_map.count(bit)) {
			a = bit2aig(not_map.at(bit)) ^ 1;
		} else
		if (and_map.count(bit)) {
			auto args = and_map.at(bit);
			int a0 = bit2aig(args.first);
			int a1 = bit2aig(args.second);
			a = mkgate(a0, a1);
		} else
		if (alias_map.count(bit)) {
			a = bit2aig(alias_map.at(bit));
		} else
		if (initstate_bits.count(bit)) {
			a = initstate_ff;
		}

		if (bit == State::Sx || bit == State::Sz)
			log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");

		log_assert(a >= 0);
		aig_map[bit] = a;
		return a;
	}

	AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool lmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
	{
		pool<SigBit> undriven_bits;
		pool<SigBit> unused_bits;

		// promote public wires
		for (auto wire : module->wires())
			if (wire->name[0] == '\\')
				sigmap.add(wire);

		// promote input wires
		for (auto wire : module->wires())
			if (wire->port_input)
				sigmap.add(wire);

		// promote output wires
		for (auto wire : module->wires())
			if (wire->port_output)
				sigmap.add(wire);

		for (auto wire : module->wires())
		{
			if (wire->attributes.count(ID::init)) {
				SigSpec initsig = sigmap(wire);
				Const initval = wire->attributes.at(ID::init);
				for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
					if (initval[i] == State::S0 || initval[i] == State::S1)
						init_map[initsig[i]] = initval[i] == State::S1;
			}

			for (int i = 0; i < GetSize(wire); i++)
			{
				SigBit wirebit(wire, i);
				SigBit bit = sigmap(wirebit);

				if (bit.wire == nullptr) {
					if (wire->port_output) {
						aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
						output_bits.insert(wirebit);
					}
					continue;
				}

				undriven_bits.insert(bit);
				unused_bits.insert(bit);

				if (wire->port_input)
					input_bits.insert(bit);

				if (wire->port_output) {
					if (bit != wirebit)
						alias_map[wirebit] = bit;
					output_bits.insert(wirebit);
				}
			}
		}

		for (auto bit : input_bits)
			undriven_bits.erase(bit);

		for (auto bit : output_bits)
			unused_bits.erase(bit);

		for (auto cell : module->cells())
		{
			if (cell->type == ID($_NOT_))
			{
				SigBit A = sigmap(cell->getPort(ID::A).as_bit());
				SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
				unused_bits.erase(A);
				undriven_bits.erase(Y);
				not_map[Y] = A;
				continue;
			}

			if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_)))
			{
				SigBit D = sigmap(cell->getPort(ID::D).as_bit());
				SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
				unused_bits.erase(D);
				undriven_bits.erase(Q);
				ff_map[Q] = D;
				continue;
			}

			if (cell->type == ID($_AND_))
			{
				SigBit A = sigmap(cell->getPort(ID::A).as_bit());
				SigBit B = sigmap(cell->getPort(ID::B).as_bit());
				SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
				unused_bits.erase(A);
				unused_bits.erase(B);
				undriven_bits.erase(Y);
				and_map[Y] = make_pair(A, B);
				continue;
			}

			if (cell->type == ID($initstate))
			{
				SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
				undriven_bits.erase(Y);
				initstate_bits.insert(Y);
				continue;
			}

			if (cell->type == ID($assert))
			{
				SigBit A = sigmap(cell->getPort(ID::A).as_bit());
				SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
				unused_bits.erase(A);
				unused_bits.erase(EN);
				asserts.push_back(make_pair(A, EN));
				continue;
			}

			if (cell->type == ID($assume))
			{
				SigBit A = sigmap(cell->getPort(ID::A).as_bit());
				SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
				unused_bits.erase(A);
				unused_bits.erase(EN);
				assumes.push_back(make_pair(A, EN));
				continue;
			}

			if (cell->type == ID($live))
			{
				SigBit A = sigmap(cell->getPort(ID::A).as_bit());
				SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
				unused_bits.erase(A);
				unused_bits.erase(EN);
				liveness.push_back(make_pair(A, EN));
				continue;
			}

			if (cell->type == ID($fair))
			{
				SigBit A = sigmap(cell->getPort(ID::A).as_bit());
				SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
				unused_bits.erase(A);
				unused_bits.erase(EN);
				fairness.push_back(make_pair(A, EN));
				continue;
			}

			if (cell->type == ID($anyconst))
			{
				for (auto bit : sigmap(cell->getPort(ID::Y))) {
					undriven_bits.erase(bit);
					ff_map[bit] = bit;
				}
				continue;
			}

			if (cell->type == ID($anyseq))
			{
				for (auto bit : sigmap(cell->getPort(ID::Y))) {
					undriven_bits.erase(bit);
					input_bits.insert(bit);
				}
				continue;
			}

			log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
		}

		for (auto bit : unused_bits)
			undriven_bits.erase(bit);

		if (!undriven_bits.empty()) {
			undriven_bits.sort();
			for (auto bit : undriven_bits) {
				log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
				input_bits.insert(bit);
			}
			log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
		}

		init_map.sort();
		input_bits.sort();
		output_bits.sort();
		not_map.sort();
		ff_map.sort();
		and_map.sort();

		aig_map[State::S0] = 0;
		aig_map[State::S1] = 1;

		for (auto bit : input_bits) {
			aig_m++, aig_i++;
			aig_map[bit] = 2*aig_m;
		}

		if (imode && input_bits.empty()) {
			aig_m++, aig_i++;
		}

		if (zinit_mode)
		{
			for (auto it : ff_map) {
				if (init_map.count(it.first))
					continue;
				aig_m++, aig_i++;
				init_inputs[it.first] = 2*aig_m;
			}
		}

		int fair_live_inputs_cnt = GetSize(liveness);
		int fair_live_inputs_m = aig_m;

		aig_m += fair_live_inputs_cnt;
		aig_i += fair_live_inputs_cnt;

		for (auto it : ff_map) {
			aig_m++, aig_l++;
			aig_map[it.first] = 2*aig_m;
			ordered_latches[it.first] = aig_l-1;
			if (init_map.count(it.first) == 0)
				aig_latchinit.push_back(2);
			else
				aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
		}

		if (!initstate_bits.empty() || !init_inputs.empty()) {
			aig_m++, aig_l++;
			initstate_ff = 2*aig_m+1;
			aig_latchinit.push_back(0);
		}

		int fair_live_latches_cnt = GetSize(fairness) + 2*GetSize(liveness);
		int fair_live_latches_m = aig_m;
		int fair_live_latches_l = aig_l;

		aig_m += fair_live_latches_cnt;
		aig_l += fair_live_latches_cnt;

		for (int i = 0; i < fair_live_latches_cnt; i++)
			aig_latchinit.push_back(0);

		if (zinit_mode)
		{
			for (auto it : ff_map)
			{
				int l = ordered_latches[it.first];

				if (aig_latchinit.at(l) == 1)
					aig_map[it.first] ^= 1;

				if (aig_latchinit.at(l) == 2)
				{
					int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
					int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
					aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
				}
			}
		}

		for (auto it : ff_map) {
			int a = bit2aig(it.second);
			int l = ordered_latches[it.first];
			if (zinit_mode && aig_latchinit.at(l) == 1)
				aig_latchin.push_back(a ^ 1);
			else
				aig_latchin.push_back(a);
		}

		if (lmode && aig_l == 0) {
			aig_m++, aig_l++;
			aig_latchinit.push_back(0);
			aig_latchin.push_back(0);
		}

		if (!initstate_bits.empty() || !init_inputs.empty())
			aig_latchin.push_back(1);

		for (auto bit : output_bits) {
			aig_o++;
			ordered_outputs[bit] = aig_o-1;
			aig_outputs.push_back(bit2aig(bit));
		}

		if (omode && output_bits.empty()) {
			aig_o++;
			aig_outputs.push_back(0);
		}

		for (auto it : asserts) {
			aig_b++;
			int bit_a = bit2aig(it.first);
			int bit_en = bit2aig(it.second);
			aig_outputs.push_back(mkgate(bit_a^1, bit_en));
		}

		if (bmode && asserts.empty()) {
			aig_b++;
			aig_outputs.push_back(0);
		}

		for (auto it : assumes) {
			aig_c++;
			int bit_a = bit2aig(it.first);
			int bit_en = bit2aig(it.second);
			aig_outputs.push_back(mkgate(bit_a^1, bit_en)^1);
		}

		for (auto it : liveness)
		{
			int input_m = ++fair_live_inputs_m;
			int latch_m1 = ++fair_live_latches_m;
			int latch_m2 = ++fair_live_latches_m;

			log_assert(GetSize(aig_latchin) == fair_live_latches_l);
			fair_live_latches_l += 2;

			int bit_a = bit2aig(it.first);
			int bit_en = bit2aig(it.second);
			int bit_s = 2*input_m;
			int bit_q1 = 2*latch_m1;
			int bit_q2 = 2*latch_m2;

			int bit_d1 = mkgate(mkgate(bit_s, bit_en)^1, bit_q1^1)^1;
			int bit_d2 = mkgate(mkgate(bit_d1, bit_a)^1, bit_q2^1)^1;

			aig_j++;
			aig_latchin.push_back(bit_d1);
			aig_latchin.push_back(bit_d2);
			aig_outputs.push_back(mkgate(bit_q1, bit_q2^1));
		}

		for (auto it : fairness)
		{
			int latch_m = ++fair_live_latches_m;

			log_assert(GetSize(aig_latchin) == fair_live_latches_l);
			fair_live_latches_l += 1;

			int bit_a = bit2aig(it.first);
			int bit_en = bit2aig(it.second);
			int bit_q = 2*latch_m;

			aig_f++;
			aig_latchin.push_back(mkgate(mkgate(bit_q^1, bit_en^1)^1, bit_a^1));
			aig_outputs.push_back(bit_q^1);
		}
	}

	void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
	{
		int aig_obc = aig_o + aig_b + aig_c;
		int aig_obcj = aig_obc + aig_j;
		int aig_obcjf = aig_obcj + aig_f;

		log_assert(aig_m == aig_i + aig_l + aig_a);
		log_assert(aig_l == GetSize(aig_latchin));
		log_assert(aig_l == GetSize(aig_latchinit));
		log_assert(aig_obcjf == GetSize(aig_outputs));

		if (miter_mode) {
			if (aig_b || aig_c || aig_j || aig_f)
				log_error("Running AIGER back-end in -miter mode, but design contains $assert, $assume, $live and/or $fair cells!\n");
			f << stringf("%s %d %d %d 0 %d %d\n", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_a, aig_o);
		} else {
			f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
			if (aig_b || aig_c || aig_j || aig_f)
				f << stringf(" %d %d %d %d", aig_b, aig_c, aig_j, aig_f);
			f << stringf("\n");
		}

		if (ascii_mode)
		{
			for (int i = 0; i < aig_i; i++)
				f << stringf("%d\n", 2*i+2);

			for (int i = 0; i < aig_l; i++) {
				if (zinit_mode || aig_latchinit.at(i) == 0)
					f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
				else if (aig_latchinit.at(i) == 1)
					f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
				else if (aig_latchinit.at(i) == 2)
					f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
			}

			for (int i = 0; i < aig_obc; i++)
				f << stringf("%d\n", aig_outputs.at(i));

			for (int i = aig_obc; i < aig_obcj; i++)
				f << stringf("1\n");

			for (int i = aig_obc; i < aig_obcj; i++)
				f << stringf("%d\n", aig_outputs.at(i));

			for (int i = aig_obcj; i < aig_obcjf; i++)
				f << stringf("%d\n", aig_outputs.at(i));

			for (int i = 0; i < aig_a; i++)
				f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
		}
		else
		{
			for (int i = 0; i < aig_l; i++) {
				if (zinit_mode || aig_latchinit.at(i) == 0)
					f << stringf("%d\n", aig_latchin.at(i));
				else if (aig_latchinit.at(i) == 1)
					f << stringf("%d 1\n", aig_latchin.at(i));
				else if (aig_latchinit.at(i) == 2)
					f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
			}

			for (int i = 0; i < aig_obc; i++)
				f << stringf("%d\n", aig_outputs.at(i));

			for (int i = aig_obc; i < aig_obcj; i++)
				f << stringf("1\n");

			for (int i = aig_obc; i < aig_obcj; i++)
				f << stringf("%d\n", aig_outputs.at(i));

			for (int i = aig_obcj; i < aig_obcjf; i++)
				f << stringf("%d\n", aig_outputs.at(i));

			for (int i = 0; i < aig_a; i++) {
				int lhs = 2*(aig_i+aig_l+i)+2;
				int rhs0 = aig_gates.at(i).first;
				int rhs1 = aig_gates.at(i).second;
				int delta0 = lhs - rhs0;
				int delta1 = rhs0 - rhs1;
				aiger_encode(f, delta0);
				aiger_encode(f, delta1);
			}
		}

		if (symbols_mode)
		{
			dict<string, vector<string>> symbols;

			for (auto wire : module->wires())
			{
				if (wire->name[0] == '$')
					continue;

				SigSpec sig = sigmap(wire);

				for (int i = 0; i < GetSize(wire); i++)
				{
					if (sig[i].wire == nullptr) {
						if (wire->port_output)
							sig[i] = SigBit(wire, i);
						else
							continue;
					}

					if (wire->port_input) {
						int a = aig_map.at(sig[i]);
						log_assert((a & 1) == 0);
						if (GetSize(wire) != 1)
							symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
						else
							symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
					}

					if (wire->port_output) {
						int o = ordered_outputs.at(SigSpec(wire, i));
						if (GetSize(wire) != 1)
							symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
						else
							symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
					}

					if (init_inputs.count(sig[i])) {
						int a = init_inputs.at(sig[i]);
						log_assert((a & 1) == 0);
						if (GetSize(wire) != 1)
							symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
						else
							symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
					}

					if (ordered_latches.count(sig[i])) {
						int l = ordered_latches.at(sig[i]);
						const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
						if (GetSize(wire) != 1)
							symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
						else
							symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
					}
				}
			}

			symbols.sort();

			for (auto &sym : symbols) {
				f << sym.first;
				std::sort(sym.second.begin(), sym.second.end());
				for (auto &s : sym.second)
					f << " " << s;
				f << std::endl;
			}
		}

		f << stringf("c\nGenerated by %s\n", yosys_version_str);
	}

	void write_map(std::ostream &f, bool verbose_map)
	{
		dict<int, string> input_lines;
		dict<int, string> init_lines;
		dict<int, string> output_lines;
		dict<int, string> latch_lines;
		dict<int, string> wire_lines;

		for (auto wire : module->wires())
		{
			if (!verbose_map && wire->name[0] == '$')
				continue;

			SigSpec sig = sigmap(wire);

			for (int i = 0; i < GetSize(wire); i++)
			{
				if (aig_map.count(sig[i]) == 0 || sig[i].wire == nullptr)
					continue;

				int a = aig_map.at(sig[i]);

				if (verbose_map)
					wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));

				if (wire->port_input) {
					log_assert((a & 1) == 0);
					input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
				}

				if (wire->port_output) {
					int o = ordered_outputs.at(sig[i]);
					output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
				}

				if (init_inputs.count(sig[i])) {
					int a = init_inputs.at(sig[i]);
					log_assert((a & 1) == 0);
					init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
				}

				if (ordered_latches.count(sig[i])) {
					int l = ordered_latches.at(sig[i]);
					if (zinit_mode && (aig_latchinit.at(l) == 1))
						latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
					else
						latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
				}
			}
		}

		input_lines.sort();
		for (auto &it : input_lines)
			f << it.second;

		init_lines.sort();
		for (auto &it : init_lines)
			f << it.second;

		output_lines.sort();
		for (auto &it : output_lines)
			f << it.second;

		latch_lines.sort();
		for (auto &it : latch_lines)
			f << it.second;

		wire_lines.sort();
		for (auto &it : wire_lines)
			f << it.second;
	}
};

struct AigerBackend : public Backend {
	AigerBackend() : Backend("aiger", "write design to AIGER file") { }
	void help() YS_OVERRIDE
	{
		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
		log("\n");
		log("    write_aiger [options] [filename]\n");
		log("\n");
		log("Write the current design to an AIGER file. The design must be flattened and\n");
		log("must not contain any cell types except $_AND_, $_NOT_, simple FF types,\n");
		log("$assert and $assume cells, and $initstate cells.\n");
		log("\n");
		log("$assert and $assume cells are converted to AIGER bad state properties and\n");
		log("invariant constraints.\n");
		log("\n");
		log("    -ascii\n");
		log("        write ASCII version of AIGER format\n");
		log("\n");
		log("    -zinit\n");
		log("        convert FFs to zero-initialized FFs, adding additional inputs for\n");
		log("        uninitialized FFs.\n");
		log("\n");
		log("    -miter\n");
		log("        design outputs are AIGER bad state properties\n");
		log("\n");
		log("    -symbols\n");
		log("        include a symbol table in the generated AIGER file\n");
		log("\n");
		log("    -map <filename>\n");
		log("        write an extra file with port and latch symbols\n");
		log("\n");
		log("    -vmap <filename>\n");
		log("        like -map, but more verbose\n");
		log("\n");
		log("    -I, -O, -B, -L\n");
		log("        If the design contains no input/output/assert/flip-flop then create one\n");
		log("        dummy input/output/bad_state-pin or latch to make the tools reading the\n");
		log("        AIGER file happy.\n");
		log("\n");
	}
	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
	{
		bool ascii_mode = false;
		bool zinit_mode = false;
		bool miter_mode = false;
		bool symbols_mode = false;
		bool verbose_map = false;
		bool imode = false;
		bool omode = false;
		bool bmode = false;
		bool lmode = false;
		std::string map_filename;

		log_header(design, "Executing AIGER backend.\n");

		size_t argidx;
		for (argidx = 1; argidx < args.size(); argidx++)
		{
			if (args[argidx] == "-ascii") {
				ascii_mode = true;
				continue;
			}
			if (args[argidx] == "-zinit") {
				zinit_mode = true;
				continue;
			}
			if (args[argidx] == "-miter") {
				miter_mode = true;
				continue;
			}
			if (args[argidx] == "-symbols") {
				symbols_mode = true;
				continue;
			}
			if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
				map_filename = args[++argidx];
				continue;
			}
			if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
				map_filename = args[++argidx];
				verbose_map = true;
				continue;
			}
			if (args[argidx] == "-I") {
				imode = true;
				continue;
			}
			if (args[argidx] == "-O") {
				omode = true;
				continue;
			}
			if (args[argidx] == "-B") {
				bmode = true;
				continue;
			}
			if (args[argidx] == "-L") {
				lmode = true;
				continue;
			}
			break;
		}
		extra_args(f, filename, args, argidx, !ascii_mode);

		Module *top_module = design->top_module();

		if (top_module == nullptr)
			log_error("Can't find top module in current design!\n");

		if (!design->selected_whole_module(top_module))
			log_cmd_error("Can't handle partially selected module %s!\n", log_id(top_module));

		if (!top_module->processes.empty())
			log_error("Found unmapped processes in module %s: unmapped processes are not supported in AIGER backend!\n", log_id(top_module));
		if (!top_module->memories.empty())
			log_error("Found unmapped memories in module %s: unmapped memories are not supported in AIGER backend!\n", log_id(top_module));

		AigerWriter writer(top_module, zinit_mode, imode, omode, bmode, lmode);