From e62ffe5b5463c91ca274b04dcc8c2c950c57fef2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 18 Jan 2017 05:28:50 +0100
Subject: Add testcase for #259

---
 testsuite/gna/issue259/testcase_ce.vhdl | 29 +++++++++++++++++++++++++++++
 testsuite/gna/issue259/testsuite.sh     | 11 +++++++++++
 2 files changed, 40 insertions(+)
 create mode 100644 testsuite/gna/issue259/testcase_ce.vhdl
 create mode 100755 testsuite/gna/issue259/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/issue259/testcase_ce.vhdl b/testsuite/gna/issue259/testcase_ce.vhdl
new file mode 100644
index 000000000..67caf02ca
--- /dev/null
+++ b/testsuite/gna/issue259/testcase_ce.vhdl
@@ -0,0 +1,29 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity Testcase_CE is
+
+port (
+    CLK          : in std_logic
+);
+end Testcase_CE;
+
+architecture RTL of Testcase_CE is
+
+    signal y : std_logic; 
+    signal x : std_logic;
+
+begin
+
+process (CLK)
+
+begin
+    if CLK'event and CLK='1' then
+
+        x <= y when false else '0'; 
+
+    end if;
+end process;
+
+end RTL;
diff --git a/testsuite/gna/issue259/testsuite.sh b/testsuite/gna/issue259/testsuite.sh
new file mode 100755
index 000000000..660861196
--- /dev/null
+++ b/testsuite/gna/issue259/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze testcase_ce.vhdl
+elab_simulate testcase_ce
+
+clean
+
+echo "Test successful"
-- 
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